Defect Challenges Grow For IC Packaging

HOREXS is a ultra thin pcb manufacturer,which produce IC substrate pcb for IC package/testing,IC assembly.

Several vendors are ramping up new inspection equipment based on infrared, optical, and X-ray technologies in an effort to reduce defects in current and future IC packages.

While all of these technologies are necessary, they also are complementary. No one tool can meet all defect inspection requirements. As a result, packaging vendors may need to buy more and different tools.

For years, packages were relatively simple. When defects cropped up in packages at various steps during manufacturing, the inspection equipment had little trouble in finding the defects because most were relatively large.

It’s a different story today. The latest chips are faster and more complex. To optimize the performance of these chips, the industry requires new and better packages with good electrical characteristics, smaller form factors, and more I/Os. In response, packaging vendors have developed an assortment of new and complex advanced package types.

As packaging becomes more complex, and is used in markets where reliability is critical, finding defects is becoming more important. But it’s also becoming more challenging as the defects are smaller and harder to find. “There are smaller features and new materials moving into high-value packaging. This drives the need for inspection with higher quality requirements,” said Pieter Vandewalle, general manager for the ICOS division at KLA.

Others agree. “More dies are driving higher-density packaging integration. More interconnects are driving finer traces and tighter bump pitches. And this complexity is driving the need toward more inspection,” said Eelco Bergman, senior director of sales and business development at ASE. “Aside from the increasing process challenges associated with the manufacture of these complex packages, there is also an increased need for in-line process control and inspection due to the high cost of yield loss associated with multiple and advanced process node devices being integrated into these packages.”

To meet these requirements, packaging vendors will likely need the traditional optical inspection equipment as well as other tool types. “As the package complexity and density increases, optical inspection alone is not enough,” Bergman said. “For many years, the packaging industry has had a range of options available, including X-ray and C-SAM (confocal scanning acoustic microscopy). But often, these tools are better suited for sample process monitoring and failure analysis than in-line process control. With the potentially high cost associated with assembly yield loss or post-assembly test or reliability failures, there is an increasing need for high-speed, in-line metrology tools — ideally with advanced machine learning analytical capabilities that can monitor a process and detect process drift on a real-time basis. That way, corrective action can be taken before that process goes out of control and defects occur. This is particularly true for high-reliability applications, such as automotive devices, where you need to detect potentially latent defects. This will likely take a range of solutions.”

Fortunately, several new inspection systems are in the works. Among them:

Onto Innovation and KLA are ramping up new optical-based inspection systems for packaging. These systems incorporate machine learning algorithms, which use fast pattern matching techniques to help locate defects.

Companies are shipping new X-ray tools.

Other technologies also are shipping.

The packaging landscape

The wafer-level packaging inspection market is projected to grow from $208 million in 2019 to about $223 million in 2020, according to Bob Johnson, an analyst with Gartner. The figures don’t include inspection systems at the die level. “Optical is still the biggest technology,” Johnson said. “That is also true for die- or package-level inspection.”

Meanwhile, there is an explosion of new applications in the market, such as 5G and AI. In addition, traditional applications, such as automotive, computing, and mobile, continue to grow.

All systems incorporate various chips, which are encapsulated or housed in IC packages. Customers have many package types to choose from. “The choice is dependent on the application, which dictates what the packaging architecture is going to look like,” said Kim Yess, executive director of WLP materials at Brewer Science.

One way to segment the packaging landscape is by interconnect type, which includes wirebond, flip-chip, wafer-level packaging (WLP), and through-silicon vias (TSVs).

Some 75% to 80% of packages are based on wire bonding, according to TechSearch. A wire bonder stitches one chip to another chip or substrate using tiny wires. Wire bonding is used for commodity and midrange packages, as well as memory stacks.

Flip-chip is used for BGAs and other packages. In flip-chip, copper bumps or pillars are formed on top of a chip. The device is flipped and mounted on a separate die or board. The bumps land on copper pads, forming electrical connections.

WLP is used for fan-out and other packages. In one example of fan-out, a memory die is stacked on a logic chip in a package. Meanwhile, TSVs are found in high-end packages like 2.5D/3D. In 2.5D/3D, dies are stacked or placed side-by-side on top of an interposer, which incorporates TSVs. The interposer acts as the bridge between the chips and a board.

Fig. 1: Key trends in packaging Source: KLA

2.5D/3D and fan-out are classified as advanced package types. Another approach involves the use of chiplets, whereby a chipmaker may have a menu of modular dies, or chiplets, in a library. Customers can mix-and-match the chiplets and integrate them in an existing advanced package type, such as 2.5D/3D, fan-out, or a new architecture.

“We service a lot of different sectors,” said Ken Molitor, chief operating officer at Quik-Pak. “Chiplets are one area that we see growing in the future. Chip-on-board, multi-chip modules, and chiplets are all on our roadmap. We see this as something that will benefit the semiconductor industry.”

Chiplets and advanced packaging could shake up the landscape. Typically, to advance a design, the industry develops an ASIC using chip scaling to fit different functions onto a single monolithic die. But scaling is becoming more difficult and expensive at each node, and not everything benefits from scaling.

Scaling remains an option for new designs. But instead of a traditional ASIC using chip scaling, advanced packaging and chiplets are becoming alternative approaches to develop a complex system-level design.

“Customers are realizing there is more than one way to develop designs,” said Walter Ng, vice president of business development at UMC. “While there may be functions of a design that requires the highest level of performance and bleeding-edge technologies, many of the other functions do not require this. Implementing those other functions as a part of a single homogeneous piece of bleeding-edge silicon may be detrimental in terms of power and cost. Cost consideration is seen in a couple different ways. If the function does not benefit from technology scaling, then the cost per mm2 is significantly higher without receiving any offsetting area benefit. The other cost consideration is at the chip level, where many of these designs are pushing on the maximum reticle size and present serious yield concerns. This is driving a renaissance to re-look at leading-edge planar nodes like 28nm/22nm. For those customers who require bleeding-edge performance, they are looking at how to partition the performance functionality, and in many cases, implementing a multi-die solution.”

In this case, a multi-die solution is another way to describe an advanced package with complex dies. The idea here is to stack devices in the vertical direction, enabling new architectures.

“Every foundry and device maker has a serious effort in heterogenous integration. There are a number of different technologies here,” said Robert Clark, senior member of the technical staff at TEL, in a recent presentation. “For 3D dimensional integration, we need heterogenous integration as well as monolithic 3D processes that will enable us to stack logic on logic and memory on logic for future technologies.”

Nonetheless, there is one common theme among all package. “It follows the die size for the most part. You have more components inside of a package. You also have smaller dies with smaller geometries inside of the package. It’s more difficult to inspect,” Quik-Pak’s Molitor said.

Chip/packaging flow

Manufacturing chips is a complex process. First, chips are processed on a wafer in a fab using various equipment. To make an advanced logic device, it takes from 600 to 1,000 process steps or more in the fab.

During the fab flow, a chipmaker must inspect the chips for defects. Tiny defects could impact chip yields or cause a product to fail.

To find defects in chips within the fab, chipmakers use optical-based inspection equipment in the production line. Chipmakers also use e-beam inspection. Both tools are detecting nanometer-size defects.

For wafer inspection, an optical inspection system uses an optical light source to illuminate a wafer. The light source falls in the deep ultraviolet (DUV) range at 193nm wavelengths. Then, the light is collected and an image is digitized, which helps find defects on the wafer.

Once the chips are fabricated in the fab, the wafer is then ready for IC packaging at a foundry or OSAT.

Each package type has a different process flow. Take fan-out, for example. “In this packaging scheme, known good dies are placed face-down on a carrier wafer, then embedded in an epoxy mold,” explained Sandy Wen, a process integration engineer at Coventor, a Lam Research Company, in a blog. “The die-mold combination forms a reconstituted wafer, which is then processed to form redistribution layers (RDLs) with bumps on the exposed die faces for ‘fan-out’ redistribution. The reconstituted wafer is subsequently diced prior to final use.”

RDLs are the copper metal interconnects that electrically connect one part of the package to another. RDLs are measured by line and space, which refer to the width and pitch of a metal trace.

There are different types of fan-out packages. For example, geared for high-end applications, high-density fan-out has more than 500 I/Os with RDLs less than 8μm line and space. At the high-end, vendors are developing fan-out with RDLs at 2μm line/space and beyond.

This is where it gets complicated. “Traditional wafer-level fan-out faces several challenges,” said Curtis Zwenger, vice president of advanced product development at Amkor. “On the processing side, issues such as die shift and molded wafer warpage have been controlled by applying process optimization techniques. However, for more advanced structures that require multiple RDL layers and finer line/space, the amount of molded wafer warpage and surface topology become critical as to not adversely impact the photo imaging processes. On the commercial side, a challenge has always been fan-out cost versus package size. As higher levels of integration are required, package size increases, and the RDL process cost increases exponentially due to the circular reconstituted wafer format.”

During the production flow, defects may crop up in the package. As fan-out and other advanced package types become more complex, the defects tend to be smaller and harder to find. This is where inspection equipment fits in—it is designed to find defects and root them out.

In the fan-out production flow, packaging houses may insert inspection equipment in the beginning of the process. Then, there are a number of inspection steps during the flow and even after the process.

Other package types may have similar or different flows. In all cases, inspection is a requirement. “Over the past 10 years, advanced packaging has introduced several processes and materials to create innovative packages and assembly technologies. Examples include fine pitch copper pillar, through mold vias, molded underfill, conformal shielding, double-sided molding and multi-layer RDL processing,” Zwenger said “Packages that incorporate such technologies cannot be assembled cost effectively unless very robust processes and state of the art in-line controls and inspection methods are used. High-resolution X-ray imaging and automatic optical inspection have made great advancements to help detect items, such as mold and underfill voids, RDL and bump defects and foreign materials. The numerous material interfaces in today’s advanced packaging make in-line defect detection essential for cost-effective, high-quality and reliable semiconductor devices.”

Fig. 2: Chip packaging flow. Source: KLA

Optical vs. X-ray inspection

Packaging houses use multiple types of inspection equipment, but the decision to use one type or another depends on the package.

Optical inspection has been used in packaging for years. Today, Camtek, KLA and Onto Innovation sell optical inspection systems for packaging. “Optical inspection is used to find any clear defects or potential latent defects that could potentially impact yield,” said Stephen Hiebert, senior director of marketing at KLA.

In operation, packages are inserted in these optical inspection systems during the production flow. A light source is illuminated in the system, which then takes images of a package from different angles as a means to find defects.

There are some major differences between optical inspection for chips in the fab and packaging. In the fab, the inspection tools are more expensive and used to find defects at the nanoscale.

In contrast, defects are larger in packages, so optical inspection is used to find defects at the micron level. These tools use light sources at the visible range, not high-end DUV sources.

Nonetheless, the next wave of packages present some challenges for the existing tools. “You have these 3D-IC or fan-out wafer-level packaging processes. They are getting more complicated. These complicated processes require complex development,” Hiebert said. “There are other trends. An obvious one is more scaling. You have smaller critical dimensions. It could be an RDL line/space. It could be a pitch for a 3D stack like a microbump pitch or hybrid bonding and a copper pad pitch. As scaling continues, the need to find smaller defect types is critical.”

There are other major defect challenges. For example, if you have one bad die in a package, the whole package is lost.

To address these challenges, vendors have developed next-generation inspection tools for packaging. For example, using a light source in the visible range, KLA’s latest defect inspection tool uses both brightfield and darkfield techniques. In brightfield imaging, light hits the sample and the system collects scattered light from the object. In darkfield imaging, the light hits the sample from an angle.

KLA’s tool is capable of finding defects at the latest dimensions. “For advanced packaging, we are talking about critical dimensions that are on the order of a micron,” Hiebert said. “An RDL might be a 2μm line and space. Advanced customers are working on 1μm line and space. The detection for sub-critical dimension defects are still possible with optical.”

KLA’s new tool provides twice the resolution and sensitivity as the previous system. It also can target select inspection areas to capture hard-to-find defects, and it incorporates machine learning algorithms for defect detection.

Others also are developing new optical-based systems. “We will launch a new product soon for high-speed sub-micron inspection and a new technology for noise suppression for multi-layer structures,” said Damon Tsai, director of inspection product management at Onto.

These new tools also will address next-generation technologies like copper hybrid bonding. Several foundries are developing this for advanced packaging. Still in R&D, hybrid bonding stacks and bonds dies using copper-to-copper interconnects. It provides more bandwidth with lower power than the existing methods of stacking and bonding.

“We see the development of hybrid bonding, including chip-to-wafer and wafer-to-wafer with I/O pitches down to 3μm and below. This requires sub-micron defect sensitivity, <10μm TSV CD measurement for overlay control, and <10μm bump height 3D inspection.” Tsai said.

The complexity of today’s advanced packages requires other inspection technology tool types. For example, optical tools are fast and used to find surface defects, but they are generally unable to see buried structures.

This is where X-ray inspection fits in. This technology can see buried structures with high resolutions. In this market, several vendors are ramping up new X-ray inspection tools for packaging.

The drawback with X-ray is speed. Nonetheless, X-ray and optical are complementary and both are used by packaging houses.

Seeking to speed up the X-ray process, SVXR has developed a system based on High Resolution Automated X-ray Inspection (HR-AXI) technology. The system is targeted for fast in-line inspection for packaging. It also makes use of machine learning for defect detection.

“X-ray can see through metal. An optical tool can only see through dielectrics or non-conductive substrates. If you want to see a void in between two pieces of metal, or a slight delamination at an interface, an optical tool is limited,” said Brennan Peterson, director of strategy at SVXR. “Fundamentally, we can see metals where the true defects occur. Things bond at the interfaces. They don’t bond at the dielectrics state. That’s really the fundamental of where an X-ray has an advantage. You can see what matters in the connection. And then you can use that data to make it better.”

There are other issues. For example, advanced packages have a multitude of bumps with hard-to-see buried solder joints. For this application, a fast X-ray inspection tool is ideal here.

Meanwhile, some are developing different inspection equipment to address various other challenges. “Advanced packaging includes various configurations of single or multiple chips, interposers, flip chips and substrates,” said Tim Skunes, vice president of R&D at CyberOptics. “They generally rely on some form of bump to make the vertical connections between these components. The bumps may be solder balls, copper pillars or microbumps, while the horizontal connections within packages are made by redistribution lines. These involve feature sizes ranging from 10μm to 100μm. As advanced packaging processes and the features they create have become smaller and more complex, the need for effective process control has increased. This need is amplified by the fact that these processes use expensive known-good die, making the cost of failure extremely high.”

For this, CyberOptics has developed an inspection/metrology unit based on phase-shift profilometry. CyberOptics’ technology, called Multi-Reflection Suppression (MRS), provides 2D and 3D inspections for bump heights, coplanarity, diameter and shape. MRS technology is designed to suppress errors caused by spurious multiple reflections from shiny and specular surfaces in packages.

On top of that, topography, step height, roughness, layer thickness and other parameters may be required for advanced packages. “Advanced packaging manufacturing processes have created an array of new measurements. For example, wafer bow and warpage measurement after stacking, bump coplanarity and TSVs measurements are just a few examples. To help reduce the total manufacturing cost of advanced packaging, hybrid metrology is becoming essential by performing multiple measurements and inspections simultaneously to enhance productivity,” said Thomas Fries, general manager of FormFactor’s FRT unit, a supplier of 3D surface measurement tools.

Conclusion

If that’s not enough, packages may require even more inspection during the flow, such as new die sorting equipment. Using both advanced optical and infrared inspection, these systems perform inspection and die sorting after the wafer-level packages are tested and diced.

Nonetheless, advanced packaging is here to stay and becoming more important. Chiplets are also a technology to watch. Both may change the landscape.

“There is an accelerated adoption of all these technologies, actually faster than we had anticipated. We expect this to continue next year as well,” KLA’s Vandewalle said.(Article from Internet)