DDRx Memory Verification in PCB Design

When doing a printed circuit board (PCB) design with DDRx memory, I observe that designers often only take care for impedance planning and length-matching.

In other article (Crosstalk matters) I had explained that Crosstalk can significantly change signal timing, so it might be wise to use a Signal Integrity (SI) planning tool for proper planning for “clearance rules” and “parallelism rules” to avoid too much of crosstalk. The term “parallelism” rule means, DRC rules for a PCB editor, to check for too long routing in parallel before reporting a DRC violation. However, by far not all PCB editors in the market can take care for such a rule.

In this article (Length Matching) I had explained that sometimes “length matching” is not sufficient and that one could use “TOF / Time Of Flight matching”. That is the case when you use routing layers with significantly different propagations delays (which essentially in dependent of surrounding dielectric properties of that layer). Again, not all PCB-Editors in market can take care for that. But still this might not be enough to do good DDRx design. Check this out.

Can you tell, whether or not this DQ signal in relation to DQS is a good one?

What are you seeing in this picture. The green curve is a differential-DQS (DQ Strobe) signal. It defines a reference point for timing measurement.

The yellow curve is a single-ended DQ data line. It looks good. Ok, has some overshoot, a little bit of ringing, but it looks monotone around certain thresholds. So Setup/Hold Times for DQ in respect to DQS is measured as shown in the pictures.

Let us look at some timing charts, for example DDR3 data sheets like (**1).

What we can read from such datasheet, essentially, a rising DQ signal must pass beyond a threshold VIH(AC) …it must stay over this threshold for a minimum amount of time tVAC… if this condition is meet, then we can measure a SETUP-time (twds DQS), if not, we have already a violation of timing.

… then DQ signal is maybe dropping below VIH(DC)… if that point is meet, we can derive a HOLD-time (or if not, then have sufficient enough HOLD-time).

This measured setup/hold values need to be validate against setup/hold requirements from datasheet tables. But hey, it is not yet as simple as that. Now think a tangent line from Vref to VIH(AC) as shown, this gives us a “Nominal Slew rate”. With this “Nominal Slew” rate we are going into the “derating tables” of the memory’s datasheet and derive positive or negative values to add to your datasheet required SETUP and HOLD times. This is called “Derating”. Only against those derated values, we have to compare the measured/simulated values.

This gets even more "complicated" when the DQ signal is not monotonic between Vref to VIH(AC). It will mean, we have to derive the "slew rate" with a different tangent line as shown.

You see the complexity of signal thresholds and timing that must be meet, in order to guarantee proper operation.

Nobody can tell me to see all this by just watching a yellow and green curve, which anyway is just one curve of thousands of cycle that a Signal Integrity simulator is analyzing in order to find a worst-case scenario. This in combination with Crosstalk consideration and varying voltage Level, maybe even with parameter sweep of the PCB-stackup.

To be frank, many people to whom I am explaining what modern signal integrity tools can automatically validate, didn’t know that a DQS/DQ, DQS/CK or CK/Address/Command lines have such complex relationship to be meet.

Fortunately, our real Hardware is quite robust and tolerant. But if you want to drive your DDRx interface to maximum Performance, having it robust, you should do simulation. Simulation will tell you what margin’s you have in your design. You might what to use a Signal Integrity tool to make this sort of automated analysis. I am not saying it is trivial to setup, but there is software in the market which helps a lot thru what they call “DDRx Wizard”.

I am experienced to use HyperLynx from Mentor a SIEMENS Business. It brings me such a DDRx Wizard. In design data that were ready to order, I had once found “sub-optimal” implemented routing in a DDR3 design within two days of extra work for Setup and simulation and that saved a re-design, the cost, but moreover weeks of time.

I also explain what design mistake got found. DQS and DQ signals are routed in bundles, which need to meet matching conditions in length/time. Now a certain trace width got selected to meet impedance requirements. But routes were going into a fine pitch BGA area. Then the designer decided to narrow down the trace width in the fine pitch area. Those narrow segments have of cause slightly different electrical characteristic. Two DQ signals got overseen for some reason and had longer "narrowed" length. In the automated verification, it came out that those signals failed in setup/hold margin compared to all the others. With this information, we reviewed the layout and found and eliminated the problem. If this had gone into production, possibly in hardware bring up all might have worked well. But in the field, maybe on a Monday, sun-shine, 70degC ambient ... it might have spontaneously failed.

  Hans Hartmann

Sources:

(**1) www.micron.com, public datasheet of DDR3 low-power SDRAM

(**) HyperLynx Software