CSP package substrate

Chip packaging is an important link in the semiconductor industry. It is a channel for interconnecting the chip with external signals, and at the same time performs multiple functions such as fixing, sealing, heat dissipation, and protection for the bare chip.

CSP package (Chip Scale Package) refers to chip-level packaging, and its package size is basically the same as the core size of the chip. Generally, the ratio of chip area to package area is about 1:1.2. CSP packaging is widely used in AP processors of consumer electronics such as mobile phones, as well as memory chips and radio frequency modules.

These chips or modules are gradually evolving towards multi-function and low power consumption. At the same time, the size is developing in the direction of lightness, thinness, shortness and smallness. It is required to improve the packaging IO density and high-speed and high-frequency performance while still maintaining the characteristics of thinness. As a result of the CSP packaging structure, the chip assembly method has evolved from WB bonding to FC flip chip or mixed assembly; single-chip packaging has also gradually evolved to multi-chip or even stacking. According to the assembly method, the industry often divides CSP packages into two categories: WBCSP and FCCSP.

CSP package substrate trend

As an important carrier of CSP packaging, the CSP substrate carries the functions of signal interconnection, mechanical support, and bottom heat dissipation.

Corresponding to the mainstream application fields of CSP packaging mentioned above, there are two mainstream evolution directions for CSP substrates. Among them, for memory and application processors, in order to support more IO interfaces and reduce the package size, the FCCSP substrate needs to be continuously thinned while increasing the circuit density, which requires thinner substrates and finer circuit processes. For RF modules, in order to obtain better signal and integration performance, the number of substrate layers continues to increase, and the application of high-frequency materials is becoming more and more extensive.

CSP substrate key process challenges

CSP substrates have four key process challenges: ultra-thin, fine lines, and multi-layer counts. At the same time, automated production is required to ensure its quality stability. In addition, micro-holes, high-frequency, high-speed and high-stable boards, various surface treatments, and solder resist are also key technologies for CSP substrates.

CSP substrate key technology

The realization path of fine circuit on CSP substrate mainly includes three processes: Tenting-subtractive method, MSAP-modified semi-additive method, and ETS-buried circuit. The achievable circuit fineness of these three processes is different, and at the same time, the cost due to the difference in complexity is different. Among them, ETS belongs to the coreless coreless substrate process, but the circuit is the most delicate.

HOREXS has introduced advanced equipment such as high-resolution automatic LDI exposure machine, vertical non-contact MSAP developing line, etc., and the minimum line width/line spacing can be 20/20um.

Ultra-thin boards are an important requirement for memory chips and wearable devices. HOREXS has the processing capability of the thinnest core plate 0.030mm. This requires the design of all equipment in the factory to have corresponding capabilities, including reducing substrate damage, creases, warping and other issues.

Two to four layers of CSP substrates can meet most requirements, but products such as radio frequency modules have high-frequency signals and high integration, and have higher requirements for the number of substrate layers. This is a great challenge under the premise that the core board is very thin. HOREXS has a mature interlayer alignment and expansion and contraction control system, and highly automated lamination-lamination process equipment, which can realize the mass production of CSP packaging substrates with up to 10 layers.

The above-mentioned fine lines and multi-layers of thin plates are the key technical challenges of CSP packaging substrates. Only a highly automated production line can achieve stable and efficient continuous production, ensuring high-quality products and fast delivery.

The important equipment of HOREXS, such as horizontal line, vertical line, exposure machine, roller coating line, etc., adopts automatic loading and unloading design, and the whole factory adopts the industry 4.0 standard, which is fully braked and intelligently manufactured. In-line design for multi-process offline production equipment, such as fully automatic customized in-line lamination process, can reduce manpower by more than 50%, and increase production efficiency by more than double. For the single-machine manual operation equipment, HOREXS has also carried out automatic upgrades. For example, the plasma process adopts an integrated automatic production design, which realizes one-button production from feeding to discharging, and can automatically call the production program and associate the substrate- Fixture-cavity information to realize parameter fool-proofing and traceability of production process information.

In the future, it is planned to promote mechanical drilling automation, final inspection VRS automation, AI and AOI/AVI technology integration, improve the defect mapping defect traceability system, import the CIM system, realize equipment processing, product traceability, quality traceability automation, and improve the digital level of the factory. Move towards informatization.