Creating a 4 bit carry look ahead adder
Mohammad Tahmid Hassan
ICs | Golden Residency Holder in the UAE| M.Sc Student at Khalifa University Check out my profile for interesting updates and projects!
The code I used for this project is as follows:
module demo8 (
input [3:0] a,
input [3:0] b,
input cin,
output [3:0] s,
output cout);
wire [3:0] p;
wire [3:0] g;
wire [3:0] cf;
assign g = a & b;
assign p = a | b;
assign cf[0] = cin;
assign cf[1] = g[0] | (cin & p[0] ) ;
assign cf[2] = g[1] | (g[0] & p[1] )| (cin & p[0] & p[1] ) ;
assign cf[3] = g[2] | (g[1] & p[2]) | (g[0] & p[1] & p[2]) | (cin & p[0] & p[1] & p[2] );
assign cout = g[3] | (g[2] & p[3])| (g[1] & p[2] & p[3]) | (g[0] & p[1] & p[2] & p[3]) | (cin & p[0] & p[1] & p[2] & p[3]);
assign s= a ^ (b ^ cf) ;
endmodule
Here, there are 4-bit inputs a and b, a single bit input in. There is a single bit output cout and a 4 bit output s. There are 3 4-bit wires p g and cf.
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a and b represent 4-bit unsigned integers. They are ANDed to give the generate signal that produces a carry over to the following bit position and they are ORed as well to give the propagate signal that is used to carry forward the carry overs from the previous bits to the next bits following the current bit.
The results of the carry generation is stored in the 4 bit reg cf to compute the sum and into the cout output used to give the MSB of the result.
Finally, a, b and cf are XORed to give the 4 bit output s, which are used to compute the remaining digits of the sum.
The config file used is :
{
"DESIGN_NAME": "demo8",
"VERILOG_FILES": "dir::src/*.v",
"CLOCK_PORT": null,
"FP_PDN_MULTILAYER": true,
"RUN_CTS": false,
"PL_RANDOM_GLB_PLACEMENT":true,
"FP_SIZING":"absolute",
"DIE_AREA":"0 0 200 200",
"PL_TARGET_DENSITY":0.65,
"FP_PDN_AUTO_ADJUST":false,
"FP_PDN_VPITCH": 25,
"FP_PDN_HPITCH": 25,
"FP_PDN_VOFFSET": 0,
"FP_PDN_HOFFSET": 0,
"DIODE_INSERTION_STRATEGY":3
}