Course: 'Advanced VHDL Verification - Made simple' - using UVVM.

UVVM has been?the fastest growing FPGA verification methodology for several years now – independent of language.?This is due to the improvement UVVM yields in both FPGA quality and development time.?This open source Library and Methodology has?the most extensive VHDL verification support available and lets you verify really complex DUTs in a very efficient manner with excellent testbench overview.?And if you have a really simple DUT, then you just use the simple parts of UVVM.

This course is an introduction to modern verification methodology in general - and to UVVM in particular.

Note that the new?UVVM functionality for Constrained Random and Functional Coverage?from October 2021 will also be included in this course.

Efficiency and quality is all a question of?overview, readability, extensibility, maintainability and reuse, - and a good architecture is the answer. This applies for both Design and Verification, and is the target for UVVM and thus also this course.

On average half the development time for an FPGA is spent on verification. It is possible to significantly reduce this time, and major reductions can be accomplished with minor adjustments. This is a pragmatic step-by-step course on how to?reduce development time and at the same time improve the quality.?For the online course - the three classroom days are spread out on 5 days - with 4,5 hours per day.

Learn modern and efficient verification methodology, using logging, alert handling, checkers, waiters, BFMs, transactions, constrained random, functional coverage, requirement tracking and specification coverage, VVCs, scoreboards, models, TLM, etc.?But even more important,?learn how to write good testbenches to achieve a better overview, readability, maintenance, extensibility, simplicity and reuse.

Architecture and Overview are key?to all of this, together with easily understandable high-level commands (transactions). This course will show you how easy it is to achieve the benefits above - given?the right architecture all the way down and a standard set of commands that are understandable "even" for SW, DSP and HW designers.

The course is 50% labs, to allow you to see for yourself how easy it is to write and understand a good testbench. The course assumes that you have a normal designer's understanding of VHDL and preferably some experience with basic verification.

The course teaches good general verification methodology, and in addition you will get a good understanding of UVVM, BFMs, VVCs, Constrained random, Requirement and Functional coverage, etc.

See course info?***Here***

See article on?Optimised Randomisation

You can get a 45 minutes?introduction to UVVM?through this?free Webinar for Mentor/Siemens?in May 2021