CMOS Technology:

Happy Morning Today Post is CMOS:

-> CMOS stands for “Complementary Metal Oxide Semiconductor” its is a type of MOSFET (Metal-Oxide Semiconductor Field Effect Transistor). And the CMOS are used in Digital Circuit, Microprocessor, Memory Chips, Batteries and other Electronics devices. CMOS have some benefits are Low Power, High Speed, High Noise Immunity.

-> This technology uses both NMOS and PMOS to realize various logic functions. Both N and P MOSFET channels are designed to have matching characteristics. Before CMOS, PMOS and NMOS logic were widely used for implementing logic gates. PMOS was then replaced by the NMOS Technology, which used to be the standard IC fabrication technology.

-> NMOS:(Pull-Down)

=> N-channel MOSFET consists of an N-type source and drain diffused on a P-type substrate. The majority carriers are electrons. When the applied voltage to the gate is high enough, the NMOS will conduct; otherwise, it will not. Since the majority carriers (electrons) travel faster than holes, NMOS are considered to be faster than PMOS.

-> PMOS (Pull-Up)

=> P-channel MOSFET also has a Source and Drain diffused on a substrate. The Source is P-type while the substrate is N-type. The majority carriers are holes. PMOS will conduct when a low voltage is applied. When a high voltage is applied to the gate, the PMOS will not conduct

CMOS

=> Since CMOS technology uses both N-type and P-type transistors to design logic functions, a signal which turns ON a transistor type is used to turn OFF the other transistor type. This eliminates the need for pull-up resistors in favor of simple switches. In CMOS logic gates N-type MOSFETs are arranged in a pull-down network between the output and the low voltage supply rail (VSS or ground) while P-type MOSFETs are in a pull-up network between the output and the higher-voltage rail (often VDD). Thus, the N-type MOSFET will be ON when the P-type MOSFET is OFF, and vice-versa. For any input pattern, one of the networks is ON and the other is OFF

-> CMOS Inverter:

The CMOS inverter is the simplest CMOS logic gate. The circuit consists of PMOS and NMOS FET. Input A serves as the gate voltage for both transistors while Y is the output

-> NMOS transistor has an input from VSS or ground and the PMOS transistor has an input from VDD. When the input (A) is low(0) the NMOS is OFF while the PMOS is ON. VDD will appear at the output through the P-channel MOSFET path. Hence, there is output (Logic 1) with the circuit pulled up to VDD. When the input is high(1) the PMOS is OFF while the NMOS is ON. The output is pulled down and is therefore low (Logic 0).

CMOS NAND Gate:

-> The 2-input NAND gate has two N-channel MOSFETs connected in series between Y (output) and GND and two P-channel MOSFETs connected in parallel between VDD and Y.

=> If either A or B is low (Logic 0), at least one of the NMOS transistors will be OFF. This breaks the path from Y to GND since the NMOS transistors are connected in series. But in this case at least one of the PMOS transistors is ON, completing a path from Y to VDD. This makes the output Y high (Logic 1). For Y to be low, both A and B should be high to ensure that both NMOS transistors are ON so that the path from Y to GND is complete. For all the other combinations of the inputs, Y will be high. The truth table of NAND logic gate is given below.

CMOS NOR Gate:

In a 2-input NOR gate, the NMOS transistors are connected in parallel while the PMOS transistors are connected in series. When at least one of the inputs is high, at least one NMOS transistor pulls the output low. The output is only high when both inputs are low.

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