CMOS Logic Gates

In CMOS technology, digital logic gates are implemented using complementary pairs of NMOS and PMOS.

NMOS: These transistors conduct when a positive voltage is applied to gate to source(voltage greaterthan threshold voltage),this will allow current to flow from drain to source.

PMOS: These transistors conduct when a negative voltage is applied to gate to source(voltage lessthan threshold voltage), this will allow current to flow from source to drain.

A PMOS transistor is connected in parallel to NMOS transistor to form a Transmission gate. In CMOS , an element which stores a logic value is called a sequential element.There are two types of sequential elements:

Latch- The contents of latches changes immediately when input changes. It's a level sensitive memory element

Flip-Flop-The contents of flip-flop will change only at rising and falling edge of enable/clock signal. It's an edge triggered memory element