Clock gating

Clock gating is the most commonly employed design technique to save dynamic power, and one can find a plethora of technical literature on it and associated techniques.Consider a system which is fed clock pulses to change its output. In most of the cases the pulses go waste as the output does not change. Thus the extra clock pulses used form apart of power dissipation rather that adding to the circuit performance. Thus there is a need of the clock gating (CG) technique which can be applied to reduce power.

At the architectural level, designer will make architectural decision to choose the clock frequency, micro-architecture of the design, how the design needs to be partitioned with respect to clock etc. In this phase, the designer will have lot of flexibility to reduce the overall power consumption.

The following are few major architectural low power techniques used.

? Clock Gating

? Architectural Clock Gating

? Dynamic Frequency Variation

Low power techniques come at a cost of Speed, Area, and Performance penalty. Based on the application or system requirement these techniques need to be carefully adopted. In a system, the significant portion of the dynamic power is consumed by the clock distribution network. Since, the clock buffers are having highest toggle rate in the system, these clock buffers can consume 50% or even more of the dynamic power. Further they will have high drive strength to reduce the clock delay. In addition, the flip-flops receiving the clock can dissipate dynamic power even though they are not switching states. We can turn off the clocks for the transistors or flip-flops when they are not functional which will help in reducing significant portion of dynamic power consumption, while preserving the state of the transistor or flipflops. 

It is better to consider the power in all stages of the System, Software, and Hardware design. Irrespective of whether it is a system board design or chip design, system developer can use low power techniques in each phase of the design to reduce the power consumption. In the context of integrated circuit design flow, there are several stages where in which low power design techniques can be used like Requirement Specification, Architecture design, RTL development, Synthesis activities, and Physical design activities. 

Existing clock gating methods

Gating based on inactive blocks/interfaces, protocol defined states

Architectural clock gating Implementation

Software programme entry and exit

Hardware driven and exit

Mixed hardware and software