Chip Harvesting & Down-binning
Eric Sia Siew Wei
Doctor of Philosophy in Electrical & Electronic Engineering â—† Full Time Researcher â—† Graduate Research Assistant â—† PhD Scholar (YUTP) â—† Universiti Teknologi PETRONAS (UTP) â—† EX-AMD PMO, SHP2E & IP Intern â—† Malaysia
Silicon Harvesting means to collect, reinvent and repurpose it to be commercialized. Silicon Down-binning meant to convert manufacturing defects into groups called bins to be commercialized to lower-end market segments by modifying performance characteristics.
Harvesting chips could beat chip shortage chips which also reduce wastage of money. There are several types of defects where the product’s clock speed, power efficiency, temperature and stability fail to meet the design spec. Harvesting defined by engineers as feature disable by customizing SoC.
To illustrate, taking Intel CPU as example, we implemented functional validation on Intel CPU core i7, it couldn't reach stipulated performance. Thus, we would perform down-binning to disable another 2 cores and it will become Core i5 model instead.
To identify whether the chip is harvestable or not, AMD implemented Wafer Sort Test meanwhile to check if a harvestable chip is defective or not, we perform Design For Testability (DFT) test. To harvest chip when the faulty occur, engineers should not manually open the platform and take out the CPU to fix the hardware part, but preferably use Remote System Management Unit (RSMU) and Programming method to isolate and power off the broken tile. Particularly, different types of CPU configurations require different type of down-binning / down-coring.