Chip: design, manufacturing, packaging and testing

The process of producing semiconductor products includes three major links: design, manufacturing, and packaging and testing.

1. IC design: It is a process of transforming the design requirements of system, logic and performance into a specific physical layout, which mainly includes logic design, circuit design and graphic design. Make the final designed circuit diagram into a photomask, and enter the next manufacturing step. Since the design process is mainly completed by computer, the required equipment is relatively small.

2. IC manufacturing: The manufacturing process is divided into wafer manufacturing and wafer processing. The former refers to the process of using silicon dioxide raw materials to gradually prepare single crystal silicon wafers, which mainly include silicon purification -> polysilicon manufacturing -> crystal pulling -> cutting, grinding, etc. The corresponding equipment is smelting furnace, CVD equipment, Single crystal furnace and slicing machine, etc.; wafer processing refers to the process of building a complete integrated circuit chip on the prepared wafer material, which mainly includes several major processes such as coating, photolithography, etching, and ion implantation.

3. IC packaging and testing: Packaging is the last link in the semiconductor equipment manufacturing process, which mainly includes thinning/cutting, placement/interconnection, packaging, testing, etc., corresponding to cutting and thinning equipment, lead machines, bonding machines, Sorting test machine, etc. The semiconductor material modules are concentrated in a protective shell to prevent physical damage or chemical corrosion, and finally the products that pass the test will be put into downstream applications as the final product.

1. Design

Chip design is divided into front-end design and back-end design. Front-end design (also known as logical design) and back-end design (also known as physical design) do not have a unified and strict boundary, and the design related to the process is the back-end design.

1.1 Front-end design

1) System design (performance, functional requirements)

First of all, when companies are developing, they need to formulate chip specifications, just like the function list, including the specific functions and performance requirements that the chip needs to meet.

2) RTL code design (register transfer level code: behavior design, hardware description language Verilog)

Semiconductor R&D personnel need to use hardware description language (for example, Verilog HDL is one of the most popular hardware description languages in the world) to describe the function of the module in code, that is, to describe the actual hardware circuit function through the hardware description language to form Register transfer level code.

3) RTL simulation (behavior simulation)

Once the code is formed, simulation verification is needed to verify the correctness of the coding design at this time. The standard for verification is the specification established in the first step. See if the design accurately meets all the requirements in the specification. Specifications are the gold standard for correct design. Any violation or non-compliance with the specifications requires re-modification of the design and coding.

4) Logic synthesis

After the simulation verification is passed, logic synthesis is performed. The result of logic synthesis is to translate the designed hardware description language code into a gate-level netlist (a netlist is a professional and efficient information system production tool). Synthesis needs to set constraint conditions, which is the standard that you want the synthesized circuit to achieve in terms of area, timing and other target parameters.

What is synthesis? Synthesis is the process of converting/mapping the RTL-level verilog code into a circuit represented by basic gate-level units with the Design Compiler tool. The basic gate-level units are the NAND gates, NOR gates, registers and the like that we usually learn. However, these gate-level units have been made into a standard cell library, and we can directly use software to call them without the need. Call the gate-level unit yourself to build the circuit. Simply put, the Design Compiler software is the work of translation-translating the code into the actual circuit, but it is not just as simple as the translation, it involves the optimization of the circuit and the timing constraints, so that it meets the performance requirements we made. . To

Generally speaking, it is necessary to do simulation verification again after the synthesis is completed.

5) Timing simulation (STA) & functional verification

Then verify, verify the circuit in time sequence, check whether the circuit has violations of setup time and hold time. This step is called static timing analysis. Finally, it needs to be verified again, which is a functional comparison of the synthesized netlist. authenticating.

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Copyright statement: This article is the original article of the CSDN blogger "crazy_baoli", following the CC 4.0 BY-SA copyright agreement. Please attach the original source link and this statement for reprinting.

The front-end design will get the gate-level netlist circuit of the chip.

1.2 Back-end design

1) Design for testability

When it comes to back-end design, design for testability must begin. Chips often have their own test circuits inside, and the purpose of design for testability is to consider future tests when designing. If the design for testability is passed, then the layout planning can be carried out, and the layout planning can directly affect the final area of the chip.

2) Physical layout (get layout)

After the layout plan is completed, the clock signal needs to be wired separately, and then ordinary signal wiring, including the wiring between various standard cells (basic logic gate circuits).

After wiring, the parasitic parameters are extracted, due to the resistance of the wire itself, the mutual inductance between adjacent wires, and the coupling capacitor will generate signal noise, crosstalk and reflection inside the chip. These effects can cause signal integrity problems, leading to signal voltage fluctuations and changes, and if severe, signal distortion errors will result. It is very important to extract the parasitic parameters to analyze and verify the signal integrity problem again.

3) Layout physical verification (function and timing verification)

Finally, perform functional and timing verification on the physical layout of the completed wiring, and the back-end design is completed.

4) Layout (interface between design and preparation)

The physical layout verification is completed, that is, the entire chip design phase is completed, and the following is the chip manufacturing. The physical layout is delivered to the chip foundry (called Foundry) in the GDS II file format to make the actual circuit on the wafer silicon, and then package and test the chip, and then we get the chip we actually see.

The final output of integrated circuit design is the layout, and the required integrated circuit can be obtained through plate making and process tapeout.

2. Manufacturing

2.1 Wafer manufacturing (silicon->wafer)

After completing the back-end design, the chip can be manufactured. In chip manufacturing, wafers are indispensable. From silicon dioxide (SiO2) ore, such as quartz sand, a series of chemical and physical smelting methods are used to purify silicon rods, and then cut into circular monocrystalline silicon wafers. Wafer.

2.2 Mask production (mask layout ->)

In the entire process of semiconductor manufacturing, part of it is a process from layout to wafer manufacturing, that is, photomask or mask manufacturing. This part is the key part of the process connection, the most expensive part of the process, and one of the bottlenecks restricting the minimum line width.

2.3 Lithography (to form a circuit on the wafer)

The wafer has to go through processes such as metal sputtering, photoresist coating, etching technology, and photoresist removal to cover the microcircuits on the surface, so that a lot of integrated circuit chips will be formed on a wafer.

Metal sputtering: Sprinkle the metal material to be used evenly on the wafer to form a thin film.

Coating photoresist: first put the photoresist material on the wafer, pass the photomask, and hit the light beam on the unnecessary part, destroying the structure of the photoresist material. Then, use chemicals to wash away the damaged materials.

Etching technology: The silicon wafer that is not protected by photoresist is etched by ion beam.

Photoresist removal: Use the photoresist removal liquid to dissolve the remaining photoresist, so that the process is completed once.

In the end, many IC chips will be completed on a whole wafer, and then sent to packaging and testing manufacturers to cut the completed square IC chips from the wafer.

3. Packaging and testing

Packaging and testing should be two processes: packaging and testing.

1) The package is to seal the circuit (die) with plastic, leaving only the contact pins on the outside.

2) Test, also called FT (final test) is different from WS (wafer sorting), the purpose is to ensure that the performance of your product meets the design requirements when it leaves the factory.

After the integrated circuit chip is formed, it must pass rigorous testing, cutting, and then packaging. Because a chip is quite small and thin, if it is not protected externally, it will be easily scratched and damaged. In addition, because the size of the chip is small, it is not easy to manually install it on the circuit board if a larger-sized housing is not used.

After the packaging is completed, it is necessary to enter the testing stage. At this stage, it is necessary to confirm whether the packaged IC is operating normally, and it can be shipped after it is correct. At this time, a final usable chip is formed.

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Copyright statement: This article is the original article of the CSDN blogger "crazy_baoli", following the CC 4.0 BY-SA copyright agreement. Please attach the original source link and this statement for reprinting.