Check out the new features launched in UVVM
Espen Tallaksen
CEO EmLogic, Co-founder TechSeed & EmLogic, Director FPGA and Space (now hiring - see my posts)
The UVVM steering committee is proud to announce that UVVM will very soon include Functional Coverage and Advanced Randomization. These extensions are the result of the on-going ESA UVVM project.
We have got lots of requests for this kind of functionality from both UVVM users and FPGA designers who have not yet "settled" on a verification platform. For this reason - and to make Constrained Random and Functional Coverage simpler for VHDL users, we have developed Enhanced Randomisation, Optimised Randomisation and Functional Coverage and will release all of this very soon.
Overview and Readability are the most important factors in any development - be it Design or Verification.
Reading and understanding is repeated over and over again, which is why investing in readability yields a huge return on Investment.
If you look at the syntax in UVVM Enhanced Randomisation, you will immediately understand what readability is all about. "Wasting" a few characters as shown in the example below improves readability significantly for anyone.
In my presentation today at FPGA Verification Day I presented most of the new functionality and even gave a very brief introduction to Functional Coverage in general. The live presentations will be released soon from Trias. Get in touch with them to be informed when this is released. In the meantime, you could always get a PDF of my presentation from me.
I think it is important to mention here that ESA and the Norwegian Space Agency through this ESA-UVVM project are playing a very important role in helping VHDL designers speed up FPGA and ASIC development and improve their product quality! This is particularly important in Europe where 80-90% of all FPGA designers use VHDL for design and verification, and UVVM is the dominant verification methodology independent of development language.
The new functionality will be released soon on Github. We will let you know.
In the meantime, you could always check out our upcoming courses on FPGA Design and Verification. The verification course is VHDL only, whereas the design course is 90% language independent.
UVVM is an open-source verification tool developed and sponsored by leading industry actors. See uvvm.org?for more information.