CDC pulse stretcher circuit

In a case where data from high speed clock domain to low speed clock domain need to transfer / communicate efficiently without miss, in such cases one of good techniques is just stretch the data/signal upto 1.5 times clock period of low speed clock. So that it can received.

for demonstration, here 3 flops and 2 or gate used. ps1 output is 2 clk stretch where as ps2 is 4 clks stretch output.

it can seen from wf it is stretching the d signal at ps1 and ps2 output.

similarly any number of clk stretch can be obtain by adding flops and or gate.

hope you get this basic idea of cdc {F>S} solution.

stay connected, more such concepts will publish on my wall.