Case Study on things which I learned in Synthesis during my recent Project in Client Location!

Recently I had an opportunity where I had to converge 2 hard blocks in Synthesis and close timing for a complex SOC.

After a lot of failed experiments finally, I had "achieved desired end results" which I could showcase my work to the client :)

Now comes the twist in the tale, our client asked about did we pass Formality for these optimized Netlists? The answer is I didn't worry about Formal Verification and it was Failing !!

Things started getting Complex, Me being more of a Synthesis and STA engineer I have no clue about Formality! and was neither interested to learn Formality as well Since I was Comfortable in my Zones.

However, a lot of things are going on in my mind now since without Formality Passing all my hard work and efforts will go in Vain, Obviously, the best way to escape this scenario is to "Happily Give Up" by complaining RTL is not friendly for Synthesis and I cannot innovate in this Project, However, I do not want to give Excuses.

How can I prevent this scenario?

Then I started collaborating with Synopsys R&D Team and with a few of their suggestions and my personal research in Formality by taking some tips from my friends who are experts in Formal, finally, I decided to compromise on the compile recipe and started recompiling the blocks Keeping Verification in Mind. The final output Timing was Very Good but not how we expected it to be but Formality Passed :) and we delivered the netlist to the PNR team. After few days we got the feedback that Netlist which I delivered to PNR cannot be used for DFT insertion since a lot of modules got optimized during Synthesis :(

Now things are getting started to show the reality to me and my energy levels are dropping day by day due to a lot of disappointments and back-to-back failures.

Finally, I did a few more experiments and decided to preserve the DFT modules at the cost of synthesis optimization, Final result was Decent Timing results with DFT and formal aware synthesized netlists. But the Good part of this entire process is my compromised recipe for optimizing netlist gave a significant reduction in Combinational Gate count and Buffer/Inverter Count value, What does this mean to me? I can show the value in my work by saying netlist is more suitable for DFT Hold timing closure and helps in reducing congestion aspects and save a hell lot of Power Consumption. We have more space achieved now :) Even Clients appreciated my efforts not because I achieved the best results but the way I showed my Fighting Spirit, Persistence, and Integrity when challenges came up.

Below are some of the Key Takeaways from this Case study to my audience

1. Things we learn in Book may not be blinding applied in the work since a lot of Engineers collaborate in Real-Life projects and the unnecessary complexity each of them adds in RTL code may indirectly cause a nightmare for Synthesis Engineers and it will hinder Innovation and overall delays the project Cycles. As a synthesis engineer, we need to communicate this kind of issue to RTL Teams so that at least going forward in the next projects we can come up with more synthesis-friendly RTL coding and this will benefit the Overall Organization.
2. However bad the situation can be we should never lose hope and should face the scenario with a Positive Mindset. What matters ultimately is whether your work goes into the production phase of Chip or not. Doesn't matter if it is your best recipe or compromised recipe unless you add value to your clients by Hook or by Crook.
3. This is a classical example of "Forced Learning". I am forced to learn a new Tool called Formality just to prove my recipe in Synthesis. Always Respect your clients, who knows? they always have something for you to learn as a surprise :)
4. Choose your projects and companies in such a way that you are automatically forced to get out of your Comfort Zones. There is so much to explore in Life once you start facing uncertain times and disastrous situations.

Note:

In case you are wondering what techniques I might have used which worked or which might not have worked please go through my Synthesis Article which I published. Keeping both of them in Mind you can easily guess what could have gone wrong. Of course, I don't want to spoon-feed anyone.

Synthesis Article is below:

Regards

Sriharsha Pudi

STA Engineer @spicaworks