Can you approve my floor-plan?
kunal ghosh (vlsisystemdesign.com)
Co-Founder at VLSI System Design, nurturing students in semiconductors
Hey There,
Just to give you some background, picoSoC is an example SoC using PicoRV32, and PicoRV32 is a size-optimized RISC-V CPU which implements RV32IMC instruction set architecture.
Now, while I was working as Physical design engineer in my first design company, I had always pushed to spend around 30% of design cycle on having good floor-plan, because a good floor-plan will always save your design-cycle run-time, and give you far better PPA (power, performance, area)
We are starting to implement PicoSoC hierarchical physical design in about a week (more to come on this later), so pour in your ideas to make the below floor-plan a better one. You can comment or email your ideas to my personal email id [email protected]
I have made sure, the logical routes don't go over the top of any blocks. Be prepared for a follow-up webinar on this topic. First SoC planning webinar is already been done by Tim Edwards and can be found in below link:
All the best and happy learning
Proprietor
6 年I ll approve ur plan and this is ma wats app no 09066444122
Technology Sales and Business Development
6 年What floorplan? This is a schematic.
How can you create a die's floorplan without understanding the padring and how pins are defined (assuming this is an ASIC/SOC that will be used on some type of PCB? And if this is to be put on a PCB, how can you define the ASIC/SOC pinout without understanding the PCB connectors. Best and most optimal floorplans we did was starting at system level functionality/pinout (parent) and working down into smaller components (children) where the components' pinouts were "dictated" by the "parents".