Cadence Demonstrates UCIe IP Operating at 24G on 3nm Process Across Interconnect Lengths

Cadence has been a leader in die-to-die interconnect IP since 2018, when it first introduced its 40GT/s D2D solution providing unrivaled bandwidth. This trend continues with UCIe IP, where Cadence previously demonstrated 7nm UCIe IP at 16GT/s over standard package live at multiple events, and now showcases 3nm UCIe IP operating at 24GT/s across the entire range of standard interconnect distances. The well-centered, wide-open eye diagram underscores the robustness of the design.

Cadence has achieved first-pass silicon success in all its D2D test vehicles exemplifying the effectiveness of its rigorous design and extensive testing processes. The IP is validated not only for representative use cases but also across various interconnect distances, ensuring robust performance and providing users with comprehensive data across diverse scenarios from the outset.

Cadence’s extensive UCIe IP portfolio spans multiple key processes and includes both advanced and standard interconnects, catering to any die-to-die interconnect requirements. With a fully integrated subsystem IP (PHY + controller), along with a comprehensive EDA toolset and verification IP, Cadence offers a complete solution for chiplet-based designs. As an active member of the UCIe consortium, Cadence remains at the forefront of updates, contributing to and helping develop the UCIe standard.