Building a RISC-V CPU Core

It was my great pleasure to team up with the Linux Foundation and RISC-V International to deliver learning content for the hardware-curious:

Building a RISC-V CPU Core is a crash course in digital logic design and basic CPU microarchitecture. Using the Makerchip online integrated development environment (IDE), you will implement everything from logic gates to a simple, but complete, RISC-V CPU core. You will be amazed by what you can do using freely-available online tools for open source development. You will familiarize yourself with a number of emerging technologies supporting an open-source hardware ecosystem, including RISC-V, Transaction-Level Verilog, and the online Makerchip IDE.

After almost 20 years using EDA tools from the "Big-3," it's part of my mission with Redwood EDA to make circuit design more accessible. My colleagues in academia confirm my concerns that students interested in hardware are often turned off by their experience with EDA tools and change majors. I'm honored that the Linux Foundation and RISC-V International have recognized that the TL-Verilog ecosystem is answering this call.

And, BTW, for those who are not new to the game, this course will open your eyes to the new culture and set you up to learn advanced techniques in future courses or by way of other online material.

I'm enjoying watching news articles pop up today, three new ones as I typed this up. So far, I see: Linux Foundation, TechRepublic, yahoo!finance, TecHRseries, Cision PR Newswire, Sydney News Today, and ZDNet. Very cool!

Oh, yeah, here's the course. Let me know how it goes for you.