In the context of digital hardware description languages (HDLs) like Verilog and VHDL, blocking and non-blocking statements are used to describe how concurrent assignments are executed within a block of code.
- Blocking Statements:In a blocking assignment, the execution of the next statement is delayed until the current assignment is completed. The assignment is performed in a sequential manner, meaning that the right-hand side (RHS) is evaluated and assigned to the left-hand side (LHS) before moving on to the next statement.
- Blocking assignments are denoted by the "=" symbol in Verilog.Example in Verilog:always @(posedge clk) a = b; // Blocking assignmentIn this example, the value of b is assigned to a on the rising edge of the clock, and the next statement will not be executed until this assignment is completed.
- Non-Blocking Statements:In a non-blocking assignment, the RHS is evaluated and assigned to the LHS without waiting for the assignment to complete. The next statement is executed immediately.
- Non-blocking assignments are denoted by the "<=" symbol in Verilog.Example in Verilog:always @(posedge clk) a <= b; // Non-blocking assignmentIn this example, the value of b is assigned to a on the rising edge of the clock, but the execution immediately moves on to the next statement without waiting for the assignment to complete. This allows for concurrent execution of assignments.
Why use Non-Blocking Assignments:
- Non-blocking assignments are often used in scenarios where concurrent behavior is desired, such as modeling flip-flops and other sequential logic elements.
- They are commonly used in clocked always blocks to model registers in hardware designs.
Why use Blocking Assignments:
- Blocking assignments are typically used when sequential behavior is desired, such as in procedural blocks where you want each statement to complete before moving on to the next one.
In summary, the choice between blocking and non-blocking assignments depends on the intended behavior of the code and whether concurrent or sequential execution is desired in a particular context within a hardware description language.
