(B)ASIC: How does the back-end engineer deal with clocks?

One of the major differences between software and hardware is the concept of a clock. It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you will find links to the previous posts. The “ASIC FUNDAMENTALS” series of blog posts starts with “synchronous design” and the rest follows chronologically after that first post. In this post, we talk about the implications for the layout team.

Place And Route

Clocks are the basis for synchronous design. In RTL, the source code of the design that is synthesizable, there is no notion of delays for any cells. Because the code is mostly independent from the underlying technology. Previously, we looked at creating a netlist. This netlist is the technology specific design with the cells and the wires connecting them. This netlist is the input for the layout of the chip. The back-end team is handling the layout, the floor-plan, the placing of the cells and the routing. But the most important part is the clock tree. Clock Tree Synthesis (CTS) is the operation whereby the real physical routing replaces the ideal wire of one front-end netlist clock. The starting point of the clock wire goes to the first flip-flop inside the area we consider the same clock domain. Some elements are close to the input wire, some are not. Traveling more distance affects the clock skew. The same active edge doesn’t reach all flip-flops of the same clock domain at the same moment in time. To get rid of that “clock skew”, a clock tree is not just a wire. No, it is a tree of clock buffers. A buffer does not change the signal, it delays it by a pre-defined amount. Buffers balance the clock tree, making sure the active edge of the clock arrives at the same moment in time. Clock tree buffers have a certain area and they require power to operate. RTL designers ideally want the whole chip as one clock domain to avoid synchronizers. Nice and simple, but impossible for the back-end team. The number of buffers would explode, increasing area and power consumption. And On Chip Variation (OCV) requires more margin on the maximum clock frequency. Simplified, the larger area to balance, the lower the maximum frequency that is achievable. And this is just the tip of the iceberg. Experience of decades of chip design helps to architect the RTL in such a way that the back-end team is fast in achieving satisfactory Clock Tree Synthesis results. As in all ASIC design matters, experience and trade-off is our everyday reality. Very few people know the technical challenges for low power chips with crazy performance for tablets, smartphones and any wearable. The shift to software engineers trying to design hardware is great, but you can easily spot them by the huge coolers they need to get rid of the heat. Because that is the very specific benefit of ASIC designers. Anyone with a basic understanding of digital circuits can design a chip. But silicon, that goes into production, is another matter. Outsiders do not know of the complex issues and problems we solve in front-end and back-end design. These solutions give confidence the chip is ready for the field. It must be able to survive in the wild for a few years. That is the difference between an amateur with a test-chip and the professionals designing chips for your smartwatch, computer, video streamers and game consoles.

What did we learn in this post?

Clocks are special for the front-end team but also for the back-end engineers. Clock Tree Synthesis and balancing the clock tree define the actual area and the performance per Watt of the chip. Therefor, back-end engineers that understand how to keep the area small while maximizing the performance per Watt are worth more than their weight in gold. And the front-end architect or project manager sows the seed of success or failure. The partitioning of the design and the clock (and reset) strategy decides the faith of the chip. And it all starts with people. Sadly, people are like office furniture in almost all companies. Throw them out when you no longer need them. A smart observer notices the explosion of the ASIC design cost, the delays and the security issues in 2020. Correlation and causation: the excel sheet quarterly profit focussed managers replacing “expensive” seniors with low cost single-skill grunts and drones.

One quote to summarize (from the software world):

"What one programmer can do in one month, two programmers can do in two months." - Fred Brooks - devRant.

Applause for ourselves!!! ????????

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#semiconductors #asic #fpga #technology #VHDL #verilog #systemverilog

Prerequisites to this post:

1st post: What is synchronous design?

2nd post: How do we design an ASIC?

3rd post: What’s a clock?

4rd post: What are the important clock parameters?

5th post: Do we choose an internal or external clock?

6th post: How do we deal with multiple clocks?

7th post: How do synthesis and STA deal with clocks?

Comment with what you want to find out next about ASIC or FPGA design.