(B) ASIC: WHAT ARE THE IMPORTANT PARAMETERS OF A CLOCK?

One of the major differences between software and hardware is the concept of a clock. It defines the rhythm the sequential elements update inside the chip. Note that in complex System-On-Chips (SoC) there are many clock frequencies that distribute to parts of the silicon. In this post, we will take a basic look at a clock. At the bottom of this post, you will find links to the previous posts. The “ASIC FUNDAMENTALS” series of blog posts starts with “synchronous design” and the rest follows chronologically after that first post.

CLOCKS, VOLTAGES AND ELECTRONICS

In the digital design world, we work with ones and zeros. We like to keep things simple, right? In our simple world, a clock is a square wave with a high period (digital ‘1’) and a low period (digital ‘0’). Since we are working with electronics, those levels are voltages. A ‘0’ we define as “GND” (ground level) or 0V. And a ‘1’ will be the supply voltage, "Vcc”. Important to note is a DC voltage gradually drops over the length of a wire. Ideally a wire has no resistance and no capacitance but in the actual world it has a tiny resistance (R) and capacitance (C), an RC network. As a result, the high and low levels in a digital circuit have threshold voltages to account for voltage drop. For a ‘1’, the threshold is Vth, Vtl for ‘0’. Any voltage higher than Vth is a logic ‘1’ and similar, lower than Vtl is a logic ‘0’. The attentive reader realizes there is also the voltage between Vth and Vtl. Digital transitions between levels go through this voltage range we call “undefined” or ‘X’. Obviously, our simple digital engineer mind does not like undefined states. But let’s park this issue for later.

FLIP MY FLOP!

In synchronous design, our first post of the series, we looked at the sequential element to capture a single bit. The D-type flip-flop is our main sequential element of choice. We use those “edge-triggered”, this means we use the rising or falling edge of the clock as the event to capture input “D”. Usually we use the rising edge of the clock as the active edge. After a delay, output “Q” will show the value of input “D”. Hence the D-type flip-flop captures the input value and shows it on its output. This brings us to two important parameters to consider: the setup and hold time of a flip-flop:

- During the time interval prior to the active edge of the clock, the setup time, the data input must remain stable to guarantee correct operation of the flip-flop.

- During the time interval after to the active edge of the clock, the hold time, the data input must remain stable to guarantee correct operation of the flip-flop.

If we have a violation of the setup or hold requirement, we have no guarantees about the value of the flip-flop output “Q”. The output becomes undefined.

From our previous post we know what a clock duty cycle is (repeated here): The ratio between the time the clock is high versus the total period of the clock is the “duty cycle” of the clock. For example, a duty cycle of 40% means the clock is high 40% of the clock period and low for the remaining 60%. This is an important ratio to remember.

The propagation delay through the flip-flop considers the time it takes from an input to reach the output. But there are multiple inputs. A flip-flop has a delay from the asynchronous reset assertion to the output that transitions to the safe value we specified in our Hardware Description Language (HDL). The two other parameters are the clock to the output delay and the input to output delay are also parameters you find in the flip-flop specification.

The maximum frequency for a flip-flop is important, it puts a limit to the maximum performance of the logic.

The recovery time of the flip-flop specifies the minimum time that an asynchronous input (example a reset) needs to be stable after being de-asserted and before the next clock active edge. Note that we talk about de-assertion of the reset for the recovery time and about assertion for the propagation delay.

Other more advanced parameters to mention are the leakage current, supply current, input capacitance, output capacitance of a flip-flop. Since we try to keep things basic, I am not explaining those yet. It would be too much detail.

WHAT DID WE LEARN IN THIS POST?

A clock is a square wave (3) and is an essential part of synchronous design (1). Our main sequential element copies the data input value to the output on the active edge of a clock but with one crucial condition. If we don’t respect the setup and hold time requirements, our flip-flop output becomes undefined. Other parameters like the duty cycle, propagation delay, recovery time and maximum frequency are important too, but they are less crucial to the core understanding of setup and hold times in digital synchronous design. And that is a simplification we use to make multi-million gate ASICs (2).

Prerequisites to this post:

(1) 1st post: What is synchronous design

(2) 2nd post: How do we design an ASIC?

(3) 3rd post: What is a clock?

Applause for ourselves!!! ????????

(support what you like) Pet my ego with a click on the like button! ??

These articles originally appeared on my personal blog.

#semiconductors #asic #fpga #technology #VHDL #verilog #systemverilog

Comment with what you want to find out about ASIC or FPGA design. It could become my next blog post or article on Linkedin!