AXI stream m<>s interface RTL design

AXI stream m<>s interface RTL design

Manish Meshram Manish Meshram

Manish Meshram

freelancer vlsi designer at VLSIUVM

发布日期: 2021年5月24日
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?The AXI4 Stream I/F has a high grade of flexibility, it has some signals that are required and many that are optional. The following signals of the bus will be implemented in code: Clock (the AXI stream bus is synchronous) Data Ready and Valid (for data flow control) ?Tlast (end of packet).

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axi stream master test bench result waveform is shown above. From waveform and block diagram it seen that axi stream is more easy than axi slave interface. Only 3-4 signals need to manage.

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axi master to slave stream interface result waveform, here start is ready signal which is all time logic 1, so master is stream the data to slave.

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Wave form shows the working of all signals from master to slave.

The code for axi master stream along with its test bench at my GitHub space. https://github.com/vlsicad/axi-stream

Alexander Suponenko

FPGA, Vivado, Vitis IDE, Vitis HLS, QT

1 年

Good day sir, is there any code examples for Verilog AXI4-stream?

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