AXI GPIO RTL design
you can find the verilog code with test-bench at my GitHub space.
https://github.com/vlsicad/axi_gpio
Here 4 gpio bus with address at 0 4 8 C used. This is free from any IP it is standalone code can be used for gpio or any other peripheral interface.
In test bench 6 write operation done, @ 0 0 0 4 8 C, and 2 read operation done @ 0 4 location, a color waveform is mark for the same.
a part of tb is shown above, which can be alter for your convinces test values.