Autonomous Drive Computer.

If your chip architecture looks like this for #autonomous_driving, you have #seriously_failed to do an architecture study of your needs.

#Interrupts were designed, a long time ago, mostly for dealing with peripherals like Keyboard and mouse, and GPUs / network adaptors. They were mostly designed to deal via buffers and DMA at kilobytes to megabytes scale.

The principal design point of the #mSoC is to move away from the interrupt mechanisms, as in autonomous driving, the size of the data that should go through the Interrupts has been tens of GIGABYTES per seconds going via the interrupt controller, cause you a huge tax on your system bandwidth and your CPU cores. Of course, you can accelerate with DMAs, but you will still be interrupted into a non-predictable pattern that will be a headache later on, stick with me.

This architecture above, I call it the "multimedia PC like Architecture", and it is NOT something that will ever solve autonomous drive above level 3. Here is why:

Interrupts, by definitions are interrupting randomly your processing on your CPU cores, causing interaction between your cache levels, L1,L2, L3 all the way to memory with your programs running on your CPUs and your system answering to the interrupts: This is going to force you to verify and validate with a safety manual all the interactions, and all the combinations of your code, with the interrupt causing "interruption" into the scheduling of your operating system. Freedom of interference is almost impossible to demonstrate on NoC with random occupation, and impossible to demonstrate for the performance of your cores, when they are being interrupted. It gets really hard to certify a system if your system is unable to guaranty the performance level of your cores.

While it seems possible to do so, when you are going to sit down with safety engineers, you are going to realize that it would take you few centuries to write down all the interactions and verify them. Even if you set up those arbitrators (In the graph 1) properly, you will still have to certify that those interactions with the CPU, L1 to LLC are secure and safe. You are basically asking your validation team and safety team to exhaustively validate the universe ... As I always say: "Good luck with that, see you in 2450".

The #mSoC is solving this problem, it makes sure that there is not an infinite set of #validation / #certification to do. More patents are coming in the pipe, an #autonomous #drive #computer cannot be a #multimedia #PC, that is the conclusion, not if you want to certify it.