Atomic Layer Processing: Building Chips One Atom at a Time

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The increasing demand for high performance compute at lowest possible cost is driving the need for faster and more power efficient chips. Integrated circuits can be made more efficient in several ways such as shrinking the size of the transistors, making/using better conductor interconnects, and tighter system-level integration. Transistor scaling has historically been the primary means of processor advancement (the transistor smallest feature has gone from sub-mm scale down to only 7nm in the state of the art processors). The transistor scaling, or the associated performance enhancement, is usually referred to as the Moore’s law. Moore’s law is an observation that the number of transistors that can be packed on an integrated circuit chip doubles nearly every two years, i.e. getting twice as much performance using a same size chip. Smaller transistors are faster, more power efficient, and use less wafer real estate. Scaling benefits have come at the cost of more complex chip designs and fabrication processes to the extend that the Moore's law is no longer a straight line. This is not surprising given the physical limitation of feature scaling. For example, beyond a few nm size for a transistor gate, quantum mechanics properties prevail, making it difficult to achieve the on/off ability with traditional designs. More complicated, yet clever, 3D designs such as FinFET have made device nodes as small as 7 nm possible. Chip makers now are exploring new design and material alternatives for next nodes, i.e. <5 nm. One design which has shown promise is gate-all-around field effect transistor (GAAFET), which essentially evolves the FinFET to the next level by having a gate wrapping around few nm thick nanowire or nanosheet channels. Regardless of the design, scaling comes with more complication for chip making. Next generation advanced chips will contain features as small as few atoms thick. It is extremely difficult to fabricate such small features with acceptable purity and dimensional variability. Processes with extreme precision are required to pattern, deposit, and etch such device components. This article highlights how atomic layer processing can be used to engineer materials at atomic level, paving the way toward building chips one atom at a time.

Atomic Layer Deposition (ALD)

ALD is essentially chemical vapor deposition (CVD) with a twist. In CVD, a mixture of gaseous precursors is introduced into the reactor chamber where they chemically react on the substrate surface to form the desired film. The by-products of the reaction are then purged out from the chamber. The thickness and uniformity is not well controlled as both reactants co-exist—reaction density, and thus the resulting film, is spatially variable. CVD is a well-established deposition method in the thin film industry. A variety of advanced CVD processes, e.g. plasma enhance CVD (PECVD), are introduced that offer better film quality and lower process temperatures. CVD, however, is not the preferred method of choice when it comes to atomic scale precision and conformal deposition. These requirements can be largely fulfilled by ALD.

ALD offers atomic scale precision by separating the reactants and limiting the chemical reactions to individual surface reactions. In the first step, the precursor is introduced where it chemically reacts with the substrate surface in a self-limiting fashion; the reaction stops when all the available surfaces are coated. The excess precursor is then purged out of the chamber, followed by the second reactant which reacts with the adsorbed precursor, again, in a self-limiting manner, forming an atomic layer of desired composition. The excess of the second reactant is then purged out of the chamber, eliminating the possibility of a “CVD” reaction in the next cycle. By repeating this cycle, a film with desired thickness can be deposited, ideally, one atomic layer at a time. Traditionally the reaction steps are separated temporally, where pulses of reactants are separated by a purge step. This mode can be rather slow and time consuming which is a bottleneck when a high throughput process is needed. Spatial ALD offers the higher throughput by separating the steps spatially—where the substrate is moved between different locations and exposed to different reactants.?Temporal ALD, however, offers better control over film quality and the ultimate critical dimensions. The choice between temporal or spatial modes depends on the variability tolerance and throughput requirements.

The advantages of sequential, self-limiting, gas phase surface reactions in ALD are numerous.?First, its conformal growth mechanism is ideal for uniformly coating 3D features, deep pores, and high-aspect-ratio trenches and holes. Second, ALD films offer constant and well-controlled chemical composition in all dimensions as the result of well-controlled surface reactions. Thus, unlike CVD, where carbon impurity is common, films deposited with ALD provide much higher quality.

ALD technology has been around for over four decades. Its use in early days was limited to fundamental studies and small scale depositions. Nowadays, ALD is well established in the industry. The chip used in latest generation smart phones has most probably gone through multiple ALD steps during fabrication. In the semiconductor industry, ALD is used to deposit dielectric materials and metals. ALD is a now an essential component of multiple-patterning processes and has been central in enabling chip makers to go 3D—realizing FinFET and 3D NAND designs.

For the same reasons outlined above, ALD has attracted much attention in thin film solar cells, Li-ion batteries, catalysis, displays, space applications, microelectromechanical parts (MEMS), healthcare, and more. The prospects of ALD are limitless. For example, imagine using the precision of ALD to fabricate miniature solid-state batteries to power IoT devices, micro-robots, drug-delivery systems, wearable electronics, etc. Future developments of ALD will undoubtedly include more sophisticated processes such as area-selective ALD (AS-ALD). Selective deposition is highly attractive for the semiconductor industry which essentially allows building chips bottom-up, relaxing the need for expensive lithography steps.?ALD, along with ALE (below), will play a big role in continuing scaling in the semiconductor industry.

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A TEM image of IBM’s 5 nm nanosheet GAAFET transistors. 30 billion of these transistors can be packed on a chip of a size of a finger nail giving 40% higher performance at 75% less power consumption over the previous FinFET generation. Image scale bar is an approximation.

Atomic Layer Etching (ALE)

Process-wise, ALE is very similar to ALD— it uses sequential self-liming surface reactions here leading to material removal rather than deposition. A typical thermal ALE process involves introduction of the first reactant to modify the surface, purging out the reactor from additional reactant, followed by introduction of the second reactant which reacts with the modified surface and volatilizes it. Unlike ALD, ALE is a rather new concept, yet to be established in the industry. The semiconductor industry is investing heavily in ALE-based etch technology as a crucial process for next generation device fabrication.

The process of chip fabrication involves several steps of depositing, patterning, and etching materials to carve various device features on the chip. Etching is traditionally done either by wet or plasma processes. Plasma etch, involves a plasma – a highly energized gas containing charged particles, radicals, and other species. Plasma etch removes materials both by chemical reactions and physical sputtering. Wet etch processes remove material by solubilizing it through chemical reactions. Advances in plasma etch, in particular, have enabled device scaling for decades. The advanced chips with intricate 3D features, however, pose serious challenges to traditional plasma and wet etch processes. Plasma etch is too aggressive to etch monolayer of materials and often leads to damages to the surface (roughening) and other components (lack of selectivity). Additionally, the etch behavior is usually feature size dependent (different etch rates in holes and trenches with different sizes) and lacks the conformity needed for processing 3D components. Traditional wet etch usually uses aggressive chemicals at high temperatures and thus lacks the precise control over the etch amount and uniformity. The holy grail of etching for the next generations of devices is a process that allows fabrication of device features with atomic-scale fidelity, is feature size independent, and provides acceptable selectivity. ALE just does the most of what we need.

Thermal ALE removes materials isotopically, which is ideal for etching 3D structures. Thermal ALE may be combined with ALD or low energy, directional ion or radicals to obtain anisotropic (directional) etching.

In 2017, IBM Research Alliance unveiled the world’s first 5 nm chip that uses a new design concept known as gate-all-around field effect transistors (GAAFET). This technology uses thermal ALE to etch SiGe layers to form horizontal Si nanosheets (channels), the 3D spaces between Si nanosheets is then filled with high-k dielectric material using ALD. The realization of these GAAFETs would have not been possible without conformal coating ability of ALD and precise selective isotropic etching of ALE. The precision of ALE and ALD can be seen in the TEM micrograph shown above. Samsung recently announced an upcoming update to its process node introducing 3 nm GAAFET that uses the same design concept.

Atomic layer processing can benefit many industries. The combination of ALD and ALE can be used to access unique material fabrication capabilities not achievable with traditional technologies. All in all, atomic layer processing is a crucial “behind the scene” technology enabling the imminent connected and automated future.?

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