Asic Verification Engineer for Sweden-Europe with Min-6years

You will be working in a team who builds/verify the products for next generation Cameras. You take ownership of the verification of platform products like reference design and so.

Creating and reviewing design verification documentation/ test plans.

Designing and implementing verification and testbenches.

Creating coverage models.

Testing and debugging VHDL, Verilog, and System Verilog RTL.

Working alongside the design team to ensure the quality of the design work done along with on time delivery.

Integrating various blocks and verify the functional correctness.

Requirements – Must list (short, and real must, no order)

Minimum 6 + years' experience of ASIC and/or FPGA verification.

Block/ System/ Sub-system verification using SV+UVM.

4+ years of experience in UVM.

Experience in Python Scripting and/or C++

Ability to correct syntax and compile the code when needed.

Soft skills

Good team player with attention to detail, self-disciplined, able to manage their own time and workload, proactive and motivated.

Strong sense of responsibility and commitment, innovative thinking.

Great communication skills.

Good to have

Scripting TCL, and/or Perl

Lab measurements on FPGA platforms.