ASIC RTL vs FPGA RTL

?The biggest difference between RTL design for ASIC and RTL design for FPGA is that ASICs are custom-designed integrated circuits, while FPGAs are programmable integrated circuits.

This means that an ASIC is designed to perform a specific set of tasks, while an FPGA can be reprogrammed to perform different tasks.In terms of RTL design, this means that the design process for an ASIC is typically more constrained and specific, as the design must be tailored to the specific technology and process being used. On the other hand, an RTL design for an FPGA is more flexible, as the design can be adapted to different technology and process nodes.Another difference is that ASICs typically have higher performance and lower power consumption than FPGAs. This is because ASICs are optimized for the specific application, while FPGAs are more general-purpose.In terms of design flow, the design flow for an ASIC is typically more complex and time-consuming than for an FPGA. This is because ASICs require more design verification, testing, and optimization steps, while FPGAs can be reprogrammed more easily.Overall, the main difference between RTL design for ASIC and RTL design for FPGA is that ASICs are custom-designed for specific applications, while FPGAs are programmable and more general-purpose.

ASIC RTL

1.???? tends to have async resets usually active low (b/c iirc that is slightly more efficient in stdcells) and async styles is usually enforced

2.???? hard-macros (such as memory/fuses/analog-pieces like PLL) are usually explicitly instantiated and hierarchically pin to facilitate floorplanning later

3.???? specialty cells like clock-gating and power-domain isolation needs to be explicitly instantiated and managed. although tools sometime can alleviate a lot of the headaches

4.???? We tended to do a lot more don't touches w/ custom cells to micro-manage synthesis

o??? for e.g. we would sometimes autogen GDCAP(decouple caps that can be ECO'd into a stdcells)/FFs spare cells

o??? special care also needed to be taken for things like scan and OCC DFT (like logic to go into / out of scan mode)

5.???? DCT (Design-Compiler-Topological) tends to be fairly strict (at least back 5yrs ago) with support for synthesis features of systemverilog. So, it was mostly V2K1 and annoying fullcase+parallelcase pragma (sigh) and lots and lots of generate+parameters or worse lots of defines+ifdef...

?

?ASIC RTL often has:

·???????? manual clock gates

·???????? manually instantiated SRAM

·???????? manually instantiated clock “anchor” buffers for constraints on the clock tree

·???????? power domains. You have to take care about isolation and power up/down sequencing

·???????? more asynchronous clock domains. In combination with power domains you really have to take care about reset domain crossings

·???????? automatic and manual/custom design for testability. Scan chains, at speed testing, built-in-self-tests (BIST) for RAMs …

·???????? retention voltages and clocks for RAMs

·???????? clock frequency scaling to reduce power consumption

·???????? in general a lot more focus on power consumption, at least when it comes to big chips for mobile phones or laptops

·???????? interfacing with on-chip analog/mixed signal implementations

For FPGA RTL

1.???? tends to use more sync reset or posedge async reset and it tends to be more lose (i often see even in xilinx ip a mixture of reset styles esp when the arm interconnects are involved).

2.???? memories are usually inferred (you can manually instatiate the M20K/BRAMs but more often than not I see FPGA devs be fairly loose about the BRAM usage).

3.???? outside of IOs/MMCMs I rarely see WYSIWYG cells / micromanaged dont-touch cells

4.???? no such a thing as DFM/DFT in FPGA design. If there is an issue just rebuild (power of reprogrammability)

5.???? FPGA tools seems to be slightly better in support of newer features in SV. So I see more interfaces/packed struct usage + always_comb/always_ff + unique case.