[ASIC Design Flow] Introduction to Timing Constraints

In this topic, a quick Introduction to Timing Constraints is introduced.

Outline

1. Why Timing Constraints? How Timing Analysis?
2. ASIC Design Flow
3. Timing Constraints
4. Static Timing Analysis
5. Timing Paths
6. Clocks
7. Port Delays
8. Combinational Paths
9. False Paths
10. Multicycle Paths
11. References

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Why Timing Constraints?

Timing Constraints is an Important part of designing ASICs or FPGAs. Generally, we want to make sure that your design is functional by verification methods and to make sure that it will behave correctly after manufacturing by timing analysis.

How Timing Analysis?

There are two ways to perform Timing Analysis

1. Dynamic Timing Analysis requires a set of input vectors to check the timing characteristics of the paths in the design. If we have N inputs then we need to make 2^N simulation combinations to get full timing analysis.
2. Static Timing Analysis checks timing violations without simulations. This is faster but doesn't check functionality issues.

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ASIC Design Flow

This flow is referred to as RTL2GDSII flow and the process to generate GDSII is termed as tapeout.

The ASIC digital flow is divided into Logical & Physical flow i.e. the Frontend and Backend. I will talk about ASIC flow in brief dividing each sub-flow into 2 pieces and each piece into 4 steps.

Logical design

A- RTL Design

Specification >> System Architecture >> RTL Design>> Functional Verification

The flow starts with High-Level design Specification, the designer puts specification for Area, Speed and Power requirements.

Then the designer starts setting Chip Architecture.

RTL, Register Transfer Level, describing the functional behavior using HDL, hardware description languages, VHDL, Verilog or SystemVerilog .

Functional Verification, verifiing the functionality using simulation.

B- Synthesis

Synthesis >> DFT >> Equivalence Checking >> Static Timing Analysis

Synthesis, the first step of converting the RTL to gate netlist based on timing, power and area constraints,

DFT, this step is for preparing the design for testability. Scan insertion is a common technique that helps to make all registers in the design controllable and observable.

Equivalence Checking, this step is for verifying the functionality of gate netlist against the RTL description using formal verification techniques.

STA, static timing analysis, a method of checking the ability of the design to meet the timing requirements statically without simulation.

Here is our Concern starts

The designer is responsible of specifying 'Timing Constraints' to model how the design needs to be constrained & the STA tools check that the design meets the timing requirements.

The designer uses an industry standard format 'SDC' Synopsys Design Constraints.

STA on this stage acts as the bridge between logical and physical design

Physical design

A-Layout

Floor Planning >> Placement >> Clock Tree Synthesis >> Routing

The flow starts with Floor Planning, the logical blocks of the design are placed considering many optimization factors to account for Area, Speed and Power.

Then Placement occurs where the connections between blocks are routed.

Placement is followed by Clock Tree Synthesis to distribute the clock and reduce clock skew between different parts of the design.

Then Routing the design is the final step to generate the layout.

During the physical design, STA may be done multiple times to perform a more accurate timing analysis.

B-Tapeout

LVS >> DRC >> Signoff STA >> GDSII? release

Two steps are needed to verify the layout

LVS, Layout versus Netlist, matching the layout with the netlist generated after synthesis.

DRC, Design Rule Checking, All rules laid out by the foundry where it will be fabricated into a chip are adhered

Then

Signoff Static Timing Analysis is performed

&

Finally, GDSII release, Fabs manufacture chips based on the GDSII.

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Timing Constraints

From timing perspective, the designer creates timing constraints for synthesis which are a series of constraints applied to a given set of paths or nets that dictate the desired performance of a design. Constraints may be period, frequency, net skew, maximum delay between end points, or maximum net delay...

Again, The designer uses an industry standard format 'SDC' Synopsys Design Constraints.

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Static Timing Analysis _STA_

Again, Static Timing Analysis is a method for determining if a circuit meets timing constraints without having to simulate so it is much faster than timing-driven, gate-level simulation. EDA tools check setup, hold and removal constraints, clock gating constraints, maximum frequency and any other design rules. They take design netlist, timing libraries, delay information and timing constraints as Inputs to perform static timing analysis.

STA as well as Equivalence checking are performed in many steps in Digital design flow, after synthesis, scan, placement, clock tree synthesis or routing.

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Timing Paths

There are four timing paths as shown in the figure:

1. Input to Register path
2. Register to Output path
3. Register to Register path
4. Input to Output path

We also can divide timing constraints into 3 categories:

1. Clocking Requirements
2. Boundaries Settings
3. Timing Exceptions

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Clocks

Clock need to be defined as follow:

• Clock Source, maybe "Port", "Net" or "Pin" or "Virtual"
• Clock Period
• Duty Cycle
• Clock Skew, Uncertainty
• Clock Latency, due to clock tree propagation
• Rise & Fall time

Example on defining clocks

// clock A 10ns with 70% duty cycle
create_clock -period 10 -name ClkA -waveform {0 7} [get_ports A]

// clock B 20ns with 50% duty cycle and phase 5 ns w.r.t clock A
create_clock -period 20 -name ClkA -waveform {5 15} [get_ports A]
 

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Port Delays

The timing constraints is applied on input and output ports.The main target is to leave a budget in time for the signal outside the block. The designer should specify the time at which the inputs would be available on the block and should specify the time for which a signal travels outside the block for outputs.

Input Delay

Input arrival time should be considered in timing constraints as described in the following example

# assume that T_CLKtoQ+TM = 10ns
 
?set_input_delay -clock CLOCK -max 10 [get_ports D}

Output Delay

Output required time should be considered in timing constraints as described in the following example

# assume that TN+T_setup = 2ns
?set_output_delay -clock CLOCK -max 10 [get_ports D}

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Combinational Paths

Sometimes there are some input/output paths which are completely combinational. In such cases the designer uses set_max_delay & set_min_delay constraints. We will talk in the next topics in detail.

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False Paths

The first timing exception is the False Paths where the changes in the source inputs, registers are not affecting the destination. So we make this timing exception. Here, I will show an example illustrating the concept.

The changes on {a} and {b} are not affecting {c_d}. Setting this path as a False Path makes the Synthesis tool not to constraint this path and for STA tool to ignore any violations on this path.

?set_false_path -from [get_ports {a b}] -to [get_ports {c_d}] 

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Multi Cycle Paths

The second timing exception is for multi-cycle paths. Sometimes a designer might need to provide some additional cycles before the data is to be captured. If there is a Multicycle path then It doesn’t limit the system frequency and we make another timing exception. Here, I will show an example illustrating the concept.

The slow logic path is relaxed and waits 2 cycles to affect the output. The requirements for timing the output for Setup and Hold of {FF4} are moved 2 more cycles to reach {FF5}.

set_multicycle_path -setup 2 -from [get_ports FF4] -to [get_cells FF5]
set_multicycle_path -hold 1  -from [get_ports FF4] -to [get_cells FF5]

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1. Constraining Designs for Synthesis and Timing Analysis, Sanjay Churiwala and Sridhar Gangadharan
2. Principles of VLSI RTL Design, Sanjay Churiwala · Sapan Garg
3. The Art of Hardware Architecture, Mohit Arora
4. www.edn.com/design/integrated-circuit-design/4433229/Basics-of-multi-cycle---false-paths
5. SDC and TimeQuest API Reference Manual, Altera

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Physical design i/p files -

The inputs to PNR tools are the design netlist, design timing libraries and design constraints. Timing libraries is a database that stores complete information about input capacitances, timing arcs, etc. of the logical cells.

by Mahmoud Abdellatif & Ganesh Dharmarajula