ASIC Design CDC Check
?Clock Domain Crossing, refers to a path connecting a sequential element/flop/primary input/black box controlled by one clock domain to another sequential element/flop/primary input/black box clocked by another clock domain.
?Clocks that are synchronous concerning each other are referred to as same-domain clocks; clocks that are asynchronous to each other are in different clock domains. Edges of clocks coming from the same clock domain are always aligned for all registers in the design and for all time throughout the execution of a design.
?As a result, if setup and hold time for a flop input is honored, there is no risk in capturing the data for the flop throughout the design. On the other hand, clocks from different domains may reach different flops at slightly different times in each cycle during the execution of the design. This timing uncertainty may cause random setup and hold-time violations.
?This issue cannot be completely identified using traditional verification methods like simulation and static timing analysis. Static clock domain crossing analysis and verification is the most efficient way of verifying CDC correctness.
?There are four main problems associated with CDCs: