Apply the 80/20 principle to efficiently learn SystemVerilog

I vividly remember my career start as a verification engineer: it was in late 2011, in the cold November (this reminds me of one of my favorite songs by Guns N' Roses), in a pretty office in Belgrade. Pleasant colleagues welcomed me and showed me my office. It was very exciting for me to start the journey of becoming a verification engineer!

Soon after learning basic Linux commands - which at the time made me feel like a hacker with superpowers - and going through basic Specman training, I embarked on the journey to learn System Verilog (SV).

I opened a language manual, and after reading about 20 pages, I was overwhelmed by the amount of information and was thinking to myself, "It will take ages to read and understand this."

Of course, this kind of self-talk is not really helpful, but that's another topic. ??. Eventually, I learned SV, of course, but now, looking back, I would have it much easier if I simply knew what topics to focus on and which ones to simply ignore in the beginning.

Fast forward to today, I can easily identify 20% of the SV language manual that will allow any verification engineer to do 80% of the work. This is the Pareto principle at work, about which I wrote some time ago, and if you are interested, you can read it here.

Below are topics that, in my opinion, are crucial for understanding most of the SV. My experience shows that any junior starting their verification career should focus on these, as understanding them will bring the most value.

After these, I will list "advanced" topics, which can be left aside initially. In other words, reading the System Verilog language manual will become much faster and easier if you follow these steps.

Disclaimer: This is my opinion, of course, and based on my experience in the industry. Somebody else may have different views on how to learn SV most efficiently.

Core concepts to cover 80% of your needs

1. Basic Syntax & Semantics:

• Data types: Learn about nets (wire) and variables (reg, logic), and how they differ.
• Modules: Understand the basic module structure, including ports (input, output) and their directions.
• Continuous assignments (assign) and always blocks (always, always_ff, always_comb).

2. Procedural Statements:

• Blocking (=) and Non-blocking (<=) Assignments: Make sure to understand the difference and when to use each.
• Control Statements: Get a handle on if-else, case, loops (for, while).

3. Interfaces and Modports:

• A way to encapsulate communication protocols. Essential for modular and scalable testbench design.

4. Testbench Constructs:

• Initial and Always Blocks: Understand how and when to use them in a testbench context.
• Tasks and Functions: Know how they differ and when to use them.

5. Object-Oriented Features:

• Classes: Grasp the basics – properties, methods, constructors.
• Inheritance: Understand the concept and its application in creating layered testbenches.
• Yes, you can skip the infamous polymorphism initially and get back to it later on.

6. Randomization:

• Learn about rand(), randc(), and constraints (constraint). This is pivotal for constrained-random verification.

7. Assertions:

• Basic immediate and concurrent assertions. They're crucial for formal verification and general sanity checks in simulations.

8. Functional Coverage:

• Coverage bins, cross coverage, and understanding when you've tested "enough".

9. Inter-process Communication:

• Events: Know how different blocks can communicate and synchronize with each other.

10. File I/O:

• Basic operations to read from and write to files – useful for testbench logging and reading stimuli.

These topics encompass the core concepts that are widely used in SV for both design and verification. By focusing on these areas, you can understand and interact with most SV codebases.

Advanced topics needed in 20% of the cases

These encompass more specialized or advanced topics that may not be used as frequently in everyday design or verification but can be crucial in specific scenarios.

1.DPI (Direct Programming Interface):

• Interfacing SystemVerilog with C/C++ functions, mainly used for high-performance model simulations or integrating legacy C/C++ code.

2. Virtual Interfaces and Classes:

• Advanced OOP concepts in SystemVerilog which are important for UVM-based testbench structures.

3. Mailboxes and Semaphores:

• Advanced inter-process communication mechanisms used in complex testbenches.

4. Program Blocks:

• Used to encapsulate simulation-only procedural code, they've been largely superseded by the use of classes and tasks but still exist in older code.

5. Gate-Level Simulations:

• Including understanding of timing checks ($setup, $hold, etc.) and SDF (Standard Delay Format).

6. Configurations and Parameterization:

• config and generate constructs used for complex design hierarchy and parameterization.

7. Multi-Dimensional Arrays & Queues:

• Advanced data structures, including associative arrays and dynamic arrays.

8. Analog Mixed Signal (AMS) Constructs:

• SystemVerilog-AMS extensions for mixed-signal design and verification.

9. Property Specification Language (PSL):

• While technically a separate language, it's often embedded in SystemVerilog for formal verification properties.

10. Specialized System Tasks/Functions:

• Functions like $past, $rose, $fell, and many more are used in a very specific scenarios or with assertions.

11. Advanced Synchronization Mechanisms:

• Callbacks.

These topics, while advanced, can be invaluable in specialized cases. As you grow and interact with various parts of the language or dive deep into certain areas of design or verification, you might encounter and need to understand some of these. However, for a foundational understanding of SystemVerilog, the initial 80% should serve well.

Conclusion

Junior engineers might feel overwhelmed by the vast scope of SystemVerilog, wondering how to learn it best.

The Pareto Principle suggests a satisfying truth: not all aspects of the SV language are created equal in terms of practical utility. In fact, you don't need to know most of it to be able to do the job well.

A focused dive into just 20% of the language's constructs can enable you to navigate and manage a substantial 80% of typical verification tasks.

I know one thing: I wish I had known this when I began my verification journey, as it would have made my learning much easier and straightforward. ??