Analog Design: More than W/L

In digital design, generally most of the people work at abstraction level of gates. This is because gates are readily available as Standard Cell Library provided by foundries. These standard cells are designed to give near optimum power, speed and area in a given technology. Near and not the absolute optimum - because there are only discrete number of drive strength (like 1X, 2X, 3X etc) of gates available in the library. For a given top level design, one could make their own gates like 1.2X to optimise the top level design even further, however it is seldom done - Time to market is more precious in the industry than area and power (besides handheld applications) if speed is already achieved. Digital design is mostly driven by tools and stitching of different IP properly has become the main work. Hence, there is not much scope in area and power optimisation as it is dictated mostly by chosen IPs and capabilities of tools. Verification is what is generally the long tail in the product development now. And hence only game left is time to market. A disclaimer: I may not be aware of design tools available in the market which would customise the cells based on the need of the design.

Now, what is involved in designing optimum cells? In digital design, there is only one dimension to play with and that is the width (W) of the transistors. The length (L) is generally what is minimum possible in the given technology. Sometimes, low power Library is also available, in which length is more than minimum. However, it is same for all the transistors in a given library.

Analog design is much more than just width and length (W/L) of the transistors.

One would wonder what it could be- it is the current through the transistor. So there are three dimensions available to Analog designers to play with - Width(W), Length(L) and Current (Id).

In digital design, gates of all transistors are connected to rails (VDD or Ground). This gives maximum gate to source voltage (VGS) and hence maximum drain current during transitions for a given W/L. Maximum drain current means maximum speed. And hence it makes sense to connect rails to the gate of transistors in the digital design.

Now question arises why same is not done in the Analog Design. This would have given more bandwidth in the circuit. However, it is not done because this would almost kill the signal if gates of transistors are biased at rails.

What is a signal? Signal is basically a physical entity abstracted as voltage or current so that electronic circuit can work with it. Physical entities (like audio, video, temperature, humidity, pressure etc) are always analog in nature i.e., it can assume any real number within a given range. For example, it can take any value between -1mV to +1mV or 0 to 2mV or 2.5V-1mV to 2.5V+1mV. These three signals look different but actually they are same. Signal is identified by amount of variation and not the actual values. Like, in all three cases, the varying component is 2mV. However, its average or mid value are different - 0V, 1mV and 2.5V. Its mid value has been given a name and it is called DC bias. DC bias is not a signature of the signal as it is always constant with respect to the time. In that case, one would wonder what is the use of DC bias - why is it anyway there? DC bias is one of the levers in the hand of Analog designers to optimise processing of Analog Signal in terms of performance and power. Higher DC bias compared to actual signal amount (like DC bias of 2.5V when signal is 2mV) would generally give higher performance but it would burn more power also at the same time.

So in Analog circuits, voltage at any node or current through any branch would have two components - DC bias and signal. If DC bias is set to VDD; for example, like, gate voltage of NMOS device is VDD+/-1mV(signal), then output drain voltage would be stuck at zero for whole signal range and hence signal would be lost. And this is the reason that gates of transistors are not biased at rails in Analog circuits.

Next question is then how to decide DC bias in Analog circuits?

Let us look at a single NMOS device. This is configured such that input is Voltage (for example Gate-to-source voltage VGS) and output is current (for example drain current Id). This configuration is chosen for simplicity.

If the relationship between VGS and Id was linear, then it would have been much easier to understand and set the DC biasing. For example, let us assume,

In this case, one can choose any voltage for DC biasing. For any value of VGS, output is a true copy of input. If we give input as

then output current Id would be equal to

The new DC bias at the output is m*VDC and signal is m*A*sin(??t+Φ). Nature of signal is still sinusoidal. Frequency of sinusoidal is also same. And only amplitude is changed by NMOS device. We can always get back the original signal by dividing the output by m, and hence one can say that signal is not at all lost in gaining it up by transconductance (voltage to current) value of m. Phase change Φ is not very important here as it can be thought of just a delay in the signal.

However, unfortunately, the relationship between VGS and Id is not linear. It is in fact,

where VTH is threshold voltage of NMOS device and m is a factor depending on W/L and technology parameters. In this case, let us assume that input given is same as above, then output current would be

Phase change is ignored for simplicity. One can see that DC bias of output is

And signal is equal to

It has got two components. One is sin(??t) and other is (sin(??t))^2. We know that

So basically, output signal has one more component in terms of twice the frequency of the input. Is this acceptable?

Output is not a replica of input and one can say that signal has been lost. If that is the case, then how is MOS circuit, suitable for analog signals (similar issue is there with Bipolar device also)?

This is where VDC is cleverly used to make even non-linear MOS device to look like linear. If

i.e.,

then signal quality degradation can be minimised to an acceptable level in a given application.

There is a concept of "small signal analysis" in Analog Design. I wondered how small is small to perform small signal analysis. If there are others like me then the above write-up might throw some light on this suspense.

There is one more point to note. Since, relationship between VGS and Id is square, the gain is 'not constant' but 'a function of DC biasing' . Expression for transconductance gain (gm) is 2*m(VDC-VTH). Higher the value of (VDC-VTH), higher the gain.

It looks like, higher value of DC biasing is always advantageous. However, there is negative side-effect of it as well, apart from higher power consumption. And that is where balancing act comes into play.

One would be knowing that there are two regions of MOS device operation: Linear and Saturation. And there is a breakpoint at VDS = VGS-VTH. The characteristic is completely different from each other in these two regions. So one has to choose either linear or saturation.

In the linear operation, Id is a strong function of VDS. If linear region is selected, then Id would depend strongly on VDS as well apart from signal (contained in VGS) which would distort the output signal further. Both VDS and Id parameters are in output side, and hence their relationship shows up as an independent resistor in the output. In the linear region, since Id variation is large with respect to VDS, ΔId/ΔVDS is large and hence effective resistance (=ΔVDS/ΔId) is low. The output current Id gets multiplied by this resistance to get the output signal in terms of voltage. If this resistance is low then output signal voltage would compress which is not desirable. Because of these two demerits, linear region is not chosen in analog design.

In saturation region, Id is a very weak function of VDS. So distortion in Id due to dependency on VDS is low and output resistance is also effectively high. Both of these are desirable results and hence saturation region is always chosen for operation in Analog design.

Now, how to set VDS of the transistor so that it is in the saturation region. It is to be noted that it is not possible to set VDS of the transistor by itself. VDS of the NMOS is decided by rest of the circuit. This is because Id is a weak function of VDS (i.e., large change in VDS causes only small change in Id) in the saturation region.

Transistors are placed between rails (say VDD and GND). If a resistor is placed between VDD and drain of NMOS transistor, then it is possible to bias NMOS in saturation region. One can choose value of resistor in such a way that voltage drop across it, is VDD minus desired VDS of NMOS (say VBIAS) for bias current Id in NMOS. That is, R= (VDD-VBIAS)/Id. The voltage available for NMOS would be VDD-(VDD-VBIAS)= VBIAS. And this way, one can fix VDS of NMOS. Generally VBIAS would be kept close to VDD/2 so that output signal can have maximum swing. If NMOS gate is biased at VTH + Δ, then saturation region would start from Δ. Output can swing from Δ to VDD. There is no limit in the upper side as resistor does not change its characteristic.

However, instead of a resistor, if a PMOS is connected between VDD and drain of NMOS and gate of PMOS is connected to (VDD-(VTH+Δ)), then again it would be difficult to set VDS of NMOS. This is because PMOS can't set its VDS as well like NMOS.

But if gate and drain of PMOS is shorted, then its VDS can be set which would be close to VTH, shown above. The output allowable voltage swing is from ??n to VDD-(VTHP+??p).

In this case, allowable voltage swing is ??1 to VDD-(VTH2+??2).

Some may wonder, why does gate-drain connected device help to bias other element in the circuit? In the case of gate-drain connected device, VGS is always equal to VDS.

1. VDS=VGS

2. 0> -VTH (if VTH is a positive number). 0 is more than any negative number.

3. Adding VGS to both sides in 2, we get VGS+0 > VGS-VTH => VGS>VGS-VTH

4. Replacing VGS in LHS of 3, with VDS, as VDS=VGS from 1, we get VDS>VGS-VTH

(In case of PMOS device, VGS, VDS and VTH are negative numbers. However, condition for saturation region in PMOS is |VDS|>|VGS|-|VTH|. Hence 4 is true for gate-drain connected PMOS device as well.)

This satisfies condition for saturation region for any value of VGS. So Gate-drain connected device is always in saturation region by construction. In saturation region, drain current mainly depends on VGS. So Id_load=??CoxW/L(VGS-VTH)^2. Id is set by driver transistor - say Id_driver. So depending on W/L of load transistor, VGS is generated across it automatically in such a way that Id_driver current flows through it. VGS generated so, depends on W/L of load transistor (other parameters are technology constants). VGS = VTH + Sqrt(Id_driver/(??CoxW/L))=VTH + ??. And hence VDS of load transistor gets set to VTH+??. This is turn sets VDS of driver transistor as VDD-(VTH+??).

In summary, VGS and W/L of driver transistor sets ID of driver transistor -> ID of driver transistor sets ID of load transistor (same current would flow in driver and load transistors as they are connected in series)-> ID of load transistor and its W/L sets VGS of load transistor -> VGS of load transistor sets VDS of load transistor (VGS=VDS) -> VDS of load transistor sets VDS of driver transistor

Ideally, one would like output to swing from rail to rail so that one gets maximum gain. However, swing is decided by the VDS value for which transistor remains in saturation. Because outside that there would be sharp change in the behaviour of transistor which would add a lot of distortion in the signal. To keep transistor in saturation region, VDS>VGS-VTH.

Now, it is obvious, that if DC biasing point of VGS is large (=> VGS-VTH is large => linear range is larger and saturation region is shorter), then allowable swing in output voltage is less. Whereas we saw before that for higher gain and linearity, one has to bias VGS higher. So there is trade-off between gain, linearity and swing. There is no free lunch.

ID, VGS and W/L of transistors are inter-dependent. So it would become difficult to set one parameter independently. To simplify this, a relatively complex circuit is used to generate a reference current (independent of PVT). A reference voltage (like band-gap voltage) can be generated on-chip with good accuracy across PVT. This is because reference voltage can be generated through ratio of resistors which is very accurate on the die. However, if that voltage needs to be converted to current, then one resistor is needed. If on-chip resistor is used, then the process variation in resistor appears in current also. Generally on-chip resistor varies by +/-20%, so reference current would also vary by similar amount. Variation in Id would put constraint on voltage swing. If signal swing is small compared to power supply, i.e., if there is very large headroom and foot-room available in the circuit then even 20% variation might be acceptable. Otherwise, one has to use external precision resistor to get very accurate Id across PVT.

One more point needs to be clarified. And that is, why current is used as the reference for biasing the circuit around the chip by using current mirror and not the voltage? One reason is that if voltage (i.e, VGS) is used as the reference then Id might vary across the chip due to on-chip variation of VTH. This is not a very strong argument though, in the case where current reference anyway varies around 20%. Other reason is that capacitive (voltage) coupling is generally much stronger and more prevalent than the inductive (current) coupling in the present day chips. It may be more difficult to disturb and adulterate current line than voltage line. I don't see any other plausible reason for this. It would be interesting to see the comments of the readers on this topic.

I think, there is no straightforward way or closed form to set DC biasing as each and every performance parameters like power, gain, offset, voltage swing, frequency response, noise are dependent on DC biasing with conflicting dependencies on ID and W/L. Several iterations might be needed. Most of the times, power is sacrificed to achieve the performance.

Here is a sample list of trade-offs (not a comprehensive one by any means):

Consideration for biasing?.. headroom??

Headroom consumed by a transistor is the minimum VDS required (VDS_SAT) below which transistor goes out of saturation region. Signal range would not be able to use this range of VDS (0 to VDS_SAT in case of NMOS, VDD to VDD-VDS_SAT in case of PMOS). That is why this range of VDS voltage is called headroom consumed or eaten away by the device.

If a transistor consumes less headroom, then for a given power-supply more voltage swing can be allowed. So less headroom consumed by the device is desirable.

For a given W/L , higher ID means transistor consumes more headroom. Higher ID=> higher gm, at the same time,?Higher ID => higher VGS-VTH (linear region is bigger and saturation region is shorter) => lower swing => more headroom consumed (hence trade-off between gm and signal swing)

For a transistor biased at a given ID, higher W/L means?transistor consumes less headroom Higher W/L => lower (VGS-VTH) => higher swing => lower headroom consumed, at the same time higher W/L => higher W (L has a lower limit set by technology) => higher area (hence trade-off between signal swing and area)

Gate-drain shorted device consumes more headroom (VDS=VGS) > VTH + Δ?

VTH in the range of 0.6 – 1V , whereas Δ is in the range of 100-300mv

Consideration of biasing?.. Intrinsic gain?(=(2VA)/(VGS-VTH) VA=1/?? where ?? is channel length modulation)?

• Larger ID(for same L and W/L)=>larger VGS-VTH ? lower gain, at the same time, larger ID => larger VGS-VTH=>higher bandwidth (hence trade-off between gain and bandwidth)
• Larger W/L (for same L and ID)=> smaller VGS-VTH ? higher gain, at the same time larger W/L means larger area ( hence trade-off between gain and area)
• larger length (for same W/L and VGS-VTH i.e, same Id) => smaller λ => larger VA => higher gain however larger L and same W/L means W is larger hence area = W*L is larger (trade-off between gain and area)

Consideration of biasing?.. Intrinsic bandwidth (fT)?.. Frequency capability??

• fT called transition frequency is a measure of maximum useful frequency of the transistor when it is used as an amplifier.
• The high frequency gain is generally controlled by capacitive elements (like gate to drain capacitance Cgs). (2pi)fT=gm/cgs = (μ(VGS-VTH))/L^2
• Higher VGS-VTH for same length L ? Higher bandwidth; Higher VGS-VTH for same length L => lower gain and Higher VGS-VTH => lower swing (hence trade-off between gain, bandwidth and swing)
• Lower L ? higher bandwidth,?however lower L => higher mismatch => higher offset (hence trade off between offset and bandwidth)

Concluding Remarks:

The main design work in analog is to set Width, length and current through the transistor. These are only three parameters, but one can see how convulated they are.

However, an engineer who has got good sense of proportion .. knows what to keep and what to throw away ..knows what is strong and what is weak.. would have easy time and even shine, in his professional life. Understanding the context and simplifying it so that solution can be found out with acceptable accuracy just by pen and paper is an open secret to become a successful engineer. This is same as looking for patterns and developing intuition to break big and complex setup into digestible smaller ones without losing its basic character. But this is easier said than done.