?? Advanced Synthesis Techniques:

The line between Synthesis & Physical Design is dissolving as we move forward into the future. Few design challenges can be handled better and make more impact if we intervene during synthesis rather than resolving later in Physical Design or ECO.

Synthesis Techniques for best PPA (Power, Performance & Area):

?Performance:

??1) Register Retiming: It's difficult to decide number of pipelines at RTL stage because unknown logic depth & achievable period for critical timing paths.

1. Analyzing critical paths during logic simplification.

2 Optimizing register placement to minimize delays

3 Move registers through combinational logic chain while optimizing logic for best timing & area.

Result: Improved performance, area may increase by tiny margin. Caveat: Difficult for formal verification and multibit banking.

??2) Logic Duplication with Retiming:

1. Duplicating logic blocks

2. Retiming registers to minimize critical path delay

3. Optimizing duplicated logic for improved timing

Result: Improved performance, reduced area as well. Less tool flexibility to perform this.

?? Congestion

??3) Crossbar Logic Optimization: To reduce congestion. A crossbar is a set of SELECT_OPs that have a set of common data inputs.

1. Tool identifies crossbar structures in design.

2. Crossbar structures typically lead to congestion in circuits and can be synthesized to mux trees in congested designs to alleviate such congestion with some trade-off area.

Result: Reduced area, improved routability & timing, lower leakage.

??4) Map2Mux ??

1. Identifying multiplexer logic which can lead to congestion. Tool can implement these logic using AND/INV/OR or MUX cells.

2. Designers can guide the tool to map such logic to MUXes in compulsion

3. Connecting multiplexer select lines to original logic input signals.

Result: Reduced area, improved timing, lower power.

??5) Multi-Cycle Path Optimization: Recover Power/Leakage, Area. Multi-Cycle Path Optimization involves:

1. Identifying non-critical paths

2. Relaxing timing constraints on non-critical paths

3. Optimizing logic for reduced area

??6) Datapath Optimization:

1. Analyzing datapath logic (Arithmetic logic such as +, -, %, X, <<. >, <= etc )

2. Identifying optimization opportunities

3. Applying optimizations to minimize logic depth better logic structures. e.g. carry save adder etc.

Result: Reduced area, improved timing, lower power.

?? Other honorable mentions:

7) Sequential Logic Optimization

8) Resource Sharing

9) Finite State Machine (FSM) Optimization

10) Algebraic Simplification, Operand Isolation, Constant Folding

11) Glitch-Free Clock Domain Crossing --> power

12) Bus Optimization?Power:

13) Dynamic Power Shaping

14) IR-aware placementThese are Synopsys references. similar techniques are available with other tools as well.

? Follow Neel Doshi for more such content. Feel free to DM for more details.