Addressing the scarcity of FPGA, ASIC Verification Engineers.

Abstract:

The scarcity of skilled FPGA (Field Programmable Gate Array) and ASIC (Application-specific integrated circuit) verification engineers in the U.S. manufacturing industry presents a significant challenge and is impacting the industry's ability to meet market demands. This white paper introduces Randstad Digital’s (RD) FPGA Training Development Program (TDP) developed by our FPGA/ASIC Solutions Principal Peter Parsons as a proactive solution to address this talent shortage. The program focuses on recruiting recent college graduates, providing targeted training, and deploying engineers to client programs with a commitment to a year of service. This paper outlines the program's components, client commitments, and expectations for success, addressing the challenges and opportunities within FPGA verification engineering.

Introduction:

The shortage of FPGA and ASIC verification engineers in the U.S. manufacturing industry necessitates innovative solutions to cultivate engineering talent. The U.S. manufacturing industry continues to struggle to fill positions with ample job openings in the market.

RD responds to this challenge with a specialized training program designed to foster the growth of young engineers and address the industry's talent needs. This program is aimed at delivering you FPGA verification engineers ready to contribute to verification test generation and debugging after 6 months and fully qualified verification engineers by 1 year and also ones that can grow in to ASIC engineers down the line as your needs dictate.

Meanwhile, in the manufacturing industry, writ large, one in four women are considering leaving. Even though women represent almost half of the US workforce, less than a third of manufacturing professionals are women. As many as 2.1 million manufacturing jobs will be unfilled through 2030, particularly because of a skills gap. U.S. manufacturers surveyed believe that finding the right talent is now 36% harder than it was in 2018.

Challenges in the Industry:

You are likely already aware of the scarcity this technology sector is feeling, but we wanted to show the effort that’s going in to understanding why and how we can work together to build the FTE workforce you need to stay ahead of the game. RD’s market analysis identifies specific challenges faced by the U.S. manufacturing industry, including inadequate university training in FPGA-specific design, difficulties in cross-training software engineers for verification tasks, and rising demands for rigorous verification. These challenges are exacerbated by FPGA complexity and functional safety requirements. RD can help find a way around the bidding war for the scarce talent in the market now. Pay rates are rising rapidly, poaching is contributing to labor rate increases, and System Verilog (and UVM) is a VERY niche field, many verification engineers are home-grown inside of companies from experienced digital design engineers.

FPGA complexity has crossed a threshold and now requires rigorous verification, not just ‘code and program’ or ‘designer directed testing’. It’s difficult to cross-train SW engineers into debug-savvy verification tasking unless they have some digital design background. Current university training is limited to basic digital design and not sufficient for FPGA specific design and verification.

Where are the System Verilog/UVM Engineers?

Let’s take a look at the rankings of the Programming Languages today:

RD FPGA TDP Program Components:

The RD FPGA TDP comprises targeted recruitment, custom-designed expert-led training, and deployment of trained engineers to client programs with a one-year commitment. Emphasis is placed on recruiting recent graduates and providing intensive training to develop their skills in FPGA verification engineering.

Resource Mentorship and Management:

RD's resource mentorship and management strategies can be delivered in cohorts built to deliver the number of engineers you anticipate needing for full time deployment in a year’s time with continued mentoring.

Continuous training, career development, proactive risk identification, and mentorship programs are crucial for supporting the growth and success of the trained engineers, ensuring optimal performance.

Governance and Quality Management:

The thought leadership provided by RD explores governance and quality management within the program, stressing the importance of tracking, reporting, proactive resource planning, pipeline management, and continuous service improvement. These measures are implemented to ensure program satisfaction and success. We’ll work with you to ensure the criteria of the coursework and experience meets your needs meeting functional safety verification and traceability requirements (DO-254 etc.).

Client Commitments and Expectations for Success:

RD can work with you to outline clear expectations for success. It emphasizes RD's dedication to developing young engineering talent and addresses the critical staffing shortage in FPGA verification. The RD team can outline the steps to success and the readiness of TDP graduates to tackle FPGA verification challenges in a SystemVerilog environment with UVM methodologies. This can include requirements for knowledge of clocked logic design testing as well as design and verification skill requirements. There are various customizable requirements that can be developed with you to ensure thorough, well rounded vetting.

Here are some of the baseline technical requirements we would suggest:

?????? BS in ECE preferred

?????? BS in EE with minor or emphasis in CS with object-oriented programming

?????? undergraduate courses in logic design and digital design

?????? language training in VHDL or Verilog

?????? completion of Senior Lab class utilizing FPGA

?????? object-oriented CS class completion

?????? demonstrates a basic understanding of clocked logic design

?????? experience writing basic test benches for verification of an FPGA

?????? some System Verilog training preferred (can also be provided as part of the TDP)

Near Future Considerations:

ChatGPT (which assisted in drafting this paper) and AI are causing considerable buzz in this industry as well. Could chips be largely verified automatically in the near future? Could chips soon be designed, implemented, verified, and tested via AI from 'requirements' or other abstract sources? It is certain AI will have an impact on this industry as well, the question is how to best harness it.

Conclusion:

Randstad Engineering Solutions' FPGA Training Development Program represents a proactive and innovative approach to alleviate the scarcity of FPGA and ASIC verification engineers in the U.S. engineering industry. By providing comprehensive training and nurturing young engineering talent, RD aims to contribute to the long-term and lasting improvement of the critical staffing shortage in FPGA verification. Only through taking such forward looking steps will anyone stand a chance to get ahead of this shortage. It will take visionary leadership to position yourself for continued success.

Here are the clear steps to success we would partner on: