Accelerated Machine Learning Available from your browser using the power of FPGAs
InAccel, a pioneer in making FPGAs accessible and scalable, is providing the benefits of FPGA acceleration and utilization from your browser. Data scientists, ML engineers and HPC users can now easily deploy and manage FPGAs, speeding up compute-intense workloads and reducing total cost of ownership.
Xilinx?, the world-leader in adaptable platforms, has released as open source the Xilinx Vitis? Library includes an extensive set of open source, performance-optimized libraries that offer out-of-the-box acceleration for workloads like Deep Neural networks, Vision and Image Processing, Quantitative Finance, Database, and Data Analytics, Data Compression and more.
InAccel provides an FPGA resource manager that allows the instant deployment, scaling and virtualization of FPGAs making easier than ever the utilization of FPGAs for applications like machine learning, data processing, data analytics and many more HPC workloads. Users can deploy their application from Python, Jupyter notebooks or even terminals.
Through the JupyterHub integration, users can now enjoy all the benefits that JupyterHub provide such as easy access to computational environment for instant execution of Jupyter notebooks. At the same time, users can now enjoy the benefits of FPGAs such as lower-latency, lower execution time and much higher performance without any prior-knowledge of FPGAs. InAccel’s framework allows the use of Xilinx’s Vitis Open-Source optimized libraries or 3rd party IP cores (for machine learning, data analytics, genomics, compression, encryption and computer vision applications.)
The Accelerated Machine Learning Platform provided by InAccel’s FPGA orchestrator can be used either on-prem (e.g. supporting the powerful Xilinx Alveo card) or on the cloud. That way, users can enjoy the simplicity of the Jupyter notebooks and at the same time experience significant speedups on their applications.
Users can test for free the available libraries on the InAccel cluster on the following link:
The platform is available for demonstration purposes. Multiple users may access the available cluster with the 2 Alveo cards. If you are interested to deploy your own data center with multiple FPGA cards or run your applications on the cloud, contact us at [email protected].
Founder&CEO @ Epteck GmbH, Embedded System, Linux, BSP, Secure-boot Expert and Trainer
4 年Simply great approach, for SW engineers to cut the tough side of FPGA development. But i am wondering how Inaccel framework is divided into FPGA FW and Host PC SW? if its using Xilinx V++ compiler in background? if its using Xilinx XRT and DMA Shell to load and run? on top of these components if Inaccel Orchestrator is in FPGA or SW?