7 PCB layout precautions to avoid "stepping pitfalls" (pictures, text + case)

1. PCB power layout

Digital circuits often require discontinuous currents, so surge currents will occur for some high-speed devices.

If the power supply trace is very long, high-frequency noise will be caused due to the presence of surge current, and this high-frequency noise will be introduced into other signals.

In high-speed circuits, there will inevitably be parasitic inductance, parasitic resistance, and parasitic capacitance, so the high-frequency noise will eventually be coupled to other circuits, and the existence of parasitic inductance will also affect the maximum surge current capacity that the trace can withstand. drop, resulting in a partial voltage drop, which may disable the circuit.

Therefore, it is particularly important to add bypass capacitors in front of digital devices. The larger the capacitance, the transmission energy is limited by the transmission rate, so a large capacitor and a small capacitor are generally combined to meet the full frequency range.

Avoid hot spots: Signal vias create voids on the power and bottom layers.

Therefore, unreasonable placement of vias is likely to increase the current density in certain areas of the power or ground plane. These places where the current density increases are called hot spots.

Therefore, we must try our best to avoid this situation when setting via holes, so as to avoid the plane being cut, which will eventually lead to EMC problems.

Usually the best way to avoid hot spots is to place vias in a mesh pattern so that the current density is uniform and the planes are not isolated, so the return path will not be too long and EMC problems will not occur.

2. PCB routing angle

When laying out high-speed signal lines, bending of the signal lines should be avoided as much as possible. If you have to bend a trace, do not trace it at an acute or right angle. Instead, trace it at an obtuse angle.

When laying out high-speed signal lines, we often use serpentine lines to achieve equal lengths. The same serpentine line is also a kind of bending of the wiring.

The line width, spacing, and bending method should be selected reasonably, and the spacing should meet the 4W/1.5W rule.

3. The distance between PCB high-speed signals

If the distance between high-speed signal lines is too close, crosstalk can easily occur. Sometimes, due to layout, board and frame size, etc., the distance between our high-speed signal lines exceeds our minimum required distance. Then we can only try to increase the distance between high-speed signal lines near the bottleneck. distance. In fact, if the space allows enough, try to increase the distance between the two high-speed signal lines.

The long stub cable is equivalent to an antenna, and if not handled properly, it will cause serious EMC problems. At the same time, stub lines will also cause reflections, reducing signal integrity.

Usually when a pull-up or pull-down resistor is added to a high-speed signal line, stub lines are most likely to be generated. Generally, stub lines can be routed in daisy-chains.

As a rule of thumb, if the length of the stub line is longer than 1/10 of the wavelength, it can be used as an antenna, and this will become a problem.

The impedance value of a trace generally depends on its width and the distance between the trace and the reference plane. The wider the trace, the lower its impedance. In some interface terminals and device pads, the same principle applies.

When the pad of an interface terminal is connected to a high-speed signal line, if the pad is particularly large and the high-speed signal line is particularly narrow, the large pad will have low impedance, and the narrow trace must have high impedance. Here In this case, impedance discontinuity will appear, and impedance discontinuity will cause signal reflection.

Therefore, generally in order to solve this problem, a forbidden copper sheet is placed under the interface terminal or the large pad of the device, and the reference plane of the pad is placed on another layer to increase the impedance and make the impedance continuous.

Vias are another source of impedance discontinuities. To minimize this effect, unnecessary copper on inner layers and via connections should be removed. In fact, such an operation can be eliminated through CAD tools during design or by contacting PCB processing maternity leave to eliminate unnecessary copper and ensure the continuity of impedance.

6. PCB high-speed differential signals

For high-speed differential signal lines, we must ensure equal width and equal spacing to achieve a specific differential impedance value. Therefore, try to ensure symmetry when laying out differential signal lines.

It is forbidden to place vias or components within the differential line pair. If vias or components are placed within the differential line pair, it will cause EMC problems and also cause impedance discontinuity.

Sometimes, some high-speed differential signal lines require coupling capacitors in series. The coupling capacitor also needs to be arranged symmetrically, and the package of the coupling capacitor cannot be too large. It is recommended to use 0402, 0603 is also acceptable. It is best not to use capacitors above 0805 or side-by-side capacitors.

Usually, via holes will produce huge impedance discontinuities, so for high-speed differential signal line pairs, minimize via holes, and if via holes are to be used, arrange them symmetrically.

7. PCB signal lines are of equal length

In some high-speed signal interfaces, generally such as buses, the arrival time and delay error between signal lines need to be considered.

For example, the arrival time of all data signal lines in a set of high-speed parallel buses must be guaranteed to be within a certain time delay error to ensure the consistency of its setup time and hold time. To satisfy this need, we have to consider equal lengths.

The high-speed differential signal line must ensure strict time lag between the two signal lines, otherwise the communication is likely to fail. Therefore, in order to meet this requirement, serpentine lines can be used to achieve equal lengths, thereby meeting the time delay requirement.

The serpentine line should generally be placed at the source of the loss of length, not the far end. Only at the source can it be ensured that the signals at the positive and negative ends of the differential line are transmitted synchronously most of the time.

Trace bends are one of the sources of loss of length. For trace bends, the equal lengths should be close to the bend (<=15mm).

If there are two traces that are bent and the distance between the two is <15mm, the loss of length between the two will compensate for each other, so there is no need to perform equal length processing at this time.

Different parts of high-speed differential signal lines should be of equal length independently. Vias, series coupling capacitors and interface terminals will divide the high-speed differential signal line into two parts, so special attention should be paid at this time. They must be of equal length. Because many EDA software only focus on whether the entire trace is lost in length during DRC.

For interfaces such as LVDS display devices, there will be several pairs of differential pairs at the same time, and the timing requirements between the differential pairs are generally very strict, and the time lag requirements are very small. Therefore, for this type of differential signals, we are generally required to be in the same plane. Make compensation. Because the signal transmission speeds of different layers are different.

When some EDA software calculates the trace length, the traces inside the pad will also be included in the length calculation. If length compensation is performed at this time, the final actual result will be lost in length. Therefore, special attention should be paid at this time when using some EDA software.

At any time, if possible, always choose symmetrical routing to avoid the need to end up with snake-like routing for equal lengths.

If space permits, try to add a small loop at the source of the short differential line to achieve compensation instead of using a serpentine line to compensate.