3 mins to know chip test and Package test

Overview of chip testing

The Chip test is divided into two stages.

• One is the CP (Chip Probing) test, which is Wafer test.??
• The other is FT (Final Test), which is to Test the chip before it is packaged.?

The purpose of CP test is to screen out the bad chips before packaging, so as to save the cost of packaging.At the same time, the yield of Wafer can be more directly known.CP test to check fab factory manufacturing level.Now for the general wafer mature process, many companies save CP, in order to reduce the cost of CP test.Whether to do CP test or not is the result of comprehensive consideration of packaging cost and CP test cost.?

The closer a wafer is to the edge, the more likely it is that a die (a small square, that is, an unpackaged chip) will fail.?

As chips get bigger, testing gets more complex.ATE (Automatic Test Equipment) came into being.At present, the largest ATE company is Teradyne and Edwan. NI is also doing this, and many small companies are using NI instruments.??The famous domestic company is Changchuan Technology.?

ATE, as a device that integrates many high-precision Instruments, is naturally expensive.?

Chip testing process

Before the test, of course, there must be ATE equipment, CP test needs Probe Card, FT test needs Load board, Socckt and so on.?

The chip Design company then provides the Design Spec and Test Spec(Datasheet) to formulate the Test Plan, develop the Test procedures, and establish the Test items.?

General tests usually contain the following tests:?

1.DC parameters Test?

It mainly includes the following tests. Continuity test (also known as Open /short test) mainly checks whether the pins of the chip and the connection with the machine are intact.??The rest of the test is to check whether the DC electrical parameters are within a certain range.?

2.Continuity Test

Leakage Test (IIL/IIH)

Power Supply Current Test (IDDQ)

Other Current/Voltage Test (IOZL/IOZH, IOS, VOL/IOL, VOH/IOH)

LDO, DCDC power test.??

The pins of DUT (Device Under Test) are hung with the upper and lower protection diodes. According to the characteristics of diode single guide on and cut-off voltage, the current is drawn/pumped on the diodes, and then the voltage is tested to see whether it is within the set limit range.?

The whole process is done by INSTRUMENTS PE(Pin Electronics) in ATE.?

Digital Functional Test??

This part of the test is mainly run test vector (Pattern), pattern is the design company DFT engineers with ATPG (Auto Test Pattern Generation) tool generated.?

Pattern testing is basically adding incentives, capturing the output and comparing it to the expected value.?

orresponding to Functional Test is Structure Test, including Scan and Boundary Scan, etc. Pattern is generated based on defects and fault model generated in the process of chip manufacturing.?

The application of Structure Test can better improve the coverage.Of course, there are build-in-self tests (BIST), which are mainly tests on memory.AC Parameters Test is mainly AC Timing Tests, including Setup Time, Hold Time, Propagation Delay and other Timing checks.ADC and DAC Test is mainly a mixed digital-analog/analog Test to check whether the signal meets the expectation after the signal passes ADC/DAC, which involves a lot of signal knowledge.In general, it includes static testing and dynamic testing.Static Test -- Histogram Method (INL, DNL)Dynamic Test -- SNR, THD, SINAD In addition to the above conventional Test items, different tests may be carried out according to different chip types, such as RF Test, SerDes high-speed Test.Efuse test, etc.A basic test flow chart is as follows:

All of the tests are performed on ATE, which can take anywhere from a few seconds to tens of seconds, and because ATE is paid for by the machine (very few hyss, apple buys dozens at a time), shortening the testing time is especially important!In addition, the general chip in the mass production test, are millions or tens of millions of chips, each chip to save a second, generally speaking, the shortened time is still very considerable.?

After the test execution is complete, the ATE outputs a Datalog to show the test results.For different test items that pass or fail, they are also sorted (Bin) and finally sorted by Handler.?

Datalog schematic diagram:

Packaging Test

Encapsulation has the function of placing, fixing, sealing, protecting the chip and enhancing the electrothermal performance, and is also a bridge between the chip's internal world and the external circuit. The contacts on the chip are connected to the pins of the encapsulation shell by wires, which in turn connect to other devices through the wires on the printed board.Therefore, encapsulation test plays an important role in integrated circuits.?

Wafers manufactured in foundries undergo an electrical Test called Wafer Acceptance Test (WAT) before leaving the factory, and wafers that pass the WAT Test are sent to the packing plant.?

The wafer is first tested by Chip Probe (CP).??Due to process reasons, various manufacturing defects will be introduced, resulting in a certain amount of defective products in the bare Die on the wafer. The purpose of CP test is to find out these defective products before packaging and reduce the cost of subsequent sealing test.?

After the wafer is manufactured, the function of the chip is tested by contacting the pad on the chip with the probe, while the unqualified chip is marked and screened after cutting.?

- Kronos air floating platform for wafer cutting applications?

The probe platform consists of a loading platform, optical components and chuck, which is mainly responsible for conveying and positioning the wafer, making the wafer contact with the probe in turn to complete the test, providing automatic wafer loading and unloading, center finding, alignment and positioning, and moving the wafer according to the designed step so that the probe on the probe card can be aligned with the corresponding position of the silicon wafer for testing.?

The loading platform is the component equipment for positioning wafers or chips. It is usually designed according to the size of the wafers and has the corresponding precision mobile positioning function.??Kronos' self-developed ultra-precision air float platform is used as a loading platform with a repeatable positioning accuracy of ±50nm, providing ultra-precise mechanical movement positioning to position wafers for precise detection.?

Wafer grinding: Wafer (wafer) has just come out of the back of the thin, to achieve the thickness required for packaging.??Tape should be placed on the front side to protect the circuit area while grinding on the back.??After grinding, remove the tape.?

● Wafer cutting (Wafer Saw) : Paste wafers on blue film, then cut wafers into separate Dice, and then clean Dice.?

● Light inspection: check whether there are defective products?

● Die Attach: chip Attach, silver paste curing (prevent oxidation), lead welding.?

Package: the chip, plastic, ceramic, metal shell produced by the chip factory is packaged to protect the chip from the influence of external moisture, dust, static electricity and so on when working. The material of the Package must consider the cost and heat dissipation effect.?

Test: The prepared chips are tested on point to check whether the chips can work normally, so as to determine the reliability and yield of each chip. Usually, the Test should be carried out before packaging, and the bad chips should be removed, only the good chips should be packaged, and then the Test should be carried out after packaging to determine whether there are problems in the packaging process.?

The process of encapsulation and testing?

Packaging and testing There are many steps in packaging and testing, and different integrated circuits may have different sequences. Generally speaking, the packaging and testing steps of integrated circuits are as follows:?

Pre-package test

Before packaging, the electrical property of the crystal (Die) is tested by Probe card. < Figure I (a) > is the appearance and structure of the Probe card.?The pre-package test of integrated circuit is to input the test telecommunication number into the metal Bond pad through some pins of the probe card, and then into the CMOS in the grain. After millions of CMOS calculations, the result is output by some other pins, as shown in < FIG. 1 (b) >.?We can judge whether the grain works normally by these output telecommunication numbers. Only when the grain is normal can it be packaged, and if it is abnormal, it will be marked with red ink.?

Laser repair and post repair test

Generally, the grains contain memory, and the grains containing memory generally contain "spare memory". If the memory is found to be faulty during the test, the corresponding metal wires will be cut off by far infrared laser, and the spare memory will replace the faulty memory, and the test will be conducted again.?If the test is normal and then encapsulated, if it is not normal, it will be marked with red ink and not encapsulated.?

Die dicing and mount

A diamond knife is used to cut the grains on the wafer along the grain cutting line to form square chips, which are then glued to a plastic or ceramic envelope by Epoxy resin.??Epoxy resins have a common name of "super glue", so mucilaginous crystals are actually used to hold the wafer in place.?

Cabling encapsulation encapsulation

One end of the gold wire is pressed on the "Bond pad" around the chip with mechanical steel mouth, and the other end is pressed on the "metal connector" of the wire rack. In this way, the telecommunication number is sent to the top layer of the adhesive pad after completing the calculation in the CMOS in the basement, and then connected to the metal connector of the wire rack through the gold wire.?

Molding

Wiring encapsulation The wiring chips and connectors are placed in a mold, filled with epoxy resin, then baked and hardened to seal the chips. The casing must protect the chips from moisture and pollution.?

Trimming and forming

Place the wires on the wafer and connector in the mold, inject epoxy resin, bake and harden the wafer, and seal the wafer with a protective and heat dissipating casing. The operation of adhesive is to completely cover the wafer to protect the wafer from moisture and pollution.?

Pre-burn-in test

The purpose of pre-firing test is to ensure that the integrated circuit will not affect the work of other normal components because of short circuit or high current during pre-firing, and at the same time, the fault integrated circuit can be screened out first, so that the fault integrated circuit does not need to be pre-fired.?

Burn-in

Prefiring allows integrated circuits to operate under strict conditions of high temperature and high voltage, causing "Early failure" of faulty components.For example, a single integrated circuits may be some in multi-layer metal wire or metal column (Via), sold to the customer may use a month after failure, if too many this kind of situation will cause the company reputation damaged, return will cause loss of money, so the factory before in integrated circuits work under strict conditions of high temperature and high voltage,To make the malformed products early failure, and screened out first.?

Final test

Full functional testing includes complete testing to meet specifications and precise timing parameters testing to ensure that integrated circuits meet factory standards.?

Lazer Marking

The information of the manufacturer, product name, batch number and manufacturing date of the product is printed on the surface of the package shell with laser as identification mark. Laser is a high-energy beam, which can directly write the text on the package shell.

Post-package test

Test after packaging good appearance as shown in the figure below IC, IC packaging after testing is to test the electric signal, through a wire frame metal pin type IC, through the pads of gold wire transferred to stick together, again into the CMOS chip, after millions of CMOS operational results by some other gelling mat is sent out again,??Finally, it is transmitted through another gold wire to another metal pin output on the wire rack. We can judge whether the integrated circuit is working properly by the signal number of these outputs.?