10 Practical Considerations for Low Noise Amplifier Design

Low noise amplifiers (LNAs) are critical components in many RF and microwave communication systems. As the first active component in a receiver chain, the LNA sets the overall noise figure and dynamic range that cascaded stages will achieve. Therefore, optimizing the LNA design is essential for ensuring maximum receiver sensitivity and ability to detect weak signals.

This article provides an overview of 10 major considerations when designing and optimizing low noise amplifiers for performance, cost, and manufacturability. Both qualitative guidelines and quantitative analysis are presented. The focus is on providing practical insight rather than detailed mathematical derivations, to serve as a useful reference for RF/microwave engineers undertaking LNA development.

LNA Design Considerations

1. Input Impedance Matching

The first key objective is matching to the source impedance, which is typically 50 ohms. Any mismatch at the input results in reflection and signal loss, degrading noise figure. Careful impedance matching is required across the entire operating bandwidth.

There are tradeoffs to evaluate. Increasing inductance enhances input match but also loss. Higher transformer turns ratios improve match but may introduce extra windings loss if not designed properly. Input match networks should provide the maximally flat response possible versus frequency to maintain a consistent match.

2. Minimizing Noise Figure

The noise factor F describes the SNR degradation by the LNA. The noise figure NF then describes this degradation in dB:

NF = 10log(F)        

where the noise factor F is given by:

F = (SNR_in) / (SNR_out)        

The key contributors to NF are:

• Active device noise
• Passive component thermal noise
• Resistive losses

Reducing NF requires using the lowest noise transistors and minimizing losses in passive components, especially at the input matching network where their noise figure degradation impacts cascade noise figure the most.

3. Providing Enough Gain

Sufficient gain is required to overcome noise contributions of subsequent stages. The LNA sets the overall noise performance, so extra gain gives headroom to tolerate additional noise from later stages without degrading system noise figure.

15-20 dB of gain is typically targeted although requirements vary. If higher gain is needed, additional gain stages may be used, provided they do not introduce too much extra noise. There are tradeoffs between optimizing for noise figure or high gain, so performance requirements must guide design decisions.

4. Input and Output Impedance Matching

As described above, proper input impedance matching is critical for minimizing signal loss and noise figure degradation. The output match is also important for maximum power transfer. Severe mismatches at either port lead to gain and noise figure deviations from what optimal designs provide.

A conjugate match is ideal but wider bandwidths may require compromises and more complex matching networks. Matching elements themselves can introduce extra loss and noise if not designed carefully. Both input and output should be matched for stability across operating bandwidths.

5. Unconditional Stability

It is essential LNAs meet stringent stability criteria to prevent oscillations which can destroy the device or system. Key parameters to evaluate are:

The goal is achieving unconditional stability from DC to above the operating frequency range, providing margin. Instability risks damaging an LNA itself and the systems it drives. Stability must be continuously validated when iterating designs.

6. Low VSWR at Input and Output Ports

The voltage standing wave ratio (VSWR) indicates how well impedance is matched at the input and output ports. A perfect match gives a VSWR of 1:1 while higher VSWR represents more severe mismatch, leading to signal reflections and loss.

It is good practice to target VSWR below 2.0 across the operating bandwidth, although for widebands higher VSWR may be unavoidable. At minimum, the passband edges should remain below 2.0. If VSWR creeps higher, revisiting impedance matching is necessary to prevent signal degradation.

7. Proper RF Layout and Grounding

LNA layout significantly impacts performance. Good RF design practices include:

• Minimal trace lengths and vias
• Solid ground plane underneath
• Entire section encircled by ground ring
• Liberal use of via fences and stitching vias
• Separate analog and digital grounds
• Careful bypassing and decoupling

Proper layout and shielding provides low inductance signal return paths. This allows maintaining impedance match and stability while also avoiding noise coupling into sensitive circuits. The result is achieving noise and gain performance predicted by simulations.

8. Sensitivity Analysis and Monte Carlo Simulations

Component tolerances and statistical process variations ensure performance will deviate somewhat from simulations. Running sensitivity analysis and Monte Carlo simulations provides visibility into the robustness of a design against real world variability.

Key parameters to sweep include:

• Transistor S-parameters
• Passive component values
• Substrate dielectric constant
• Layer thicknesses

If sweeping across expected tolerance ranges causes major performance degradation, the design lacks sufficient margin and should be re-evaluated. Statistical simulations assess yields and guide specification setting.

9. Thermal Analysis

Self-heating of active devices under high RF drive levels may cause performance to drift from ambient temperature specifications. Thermal simulations help identify heat spreading and temperature variations across the chip. Heating effects should incorporate directional RF flow and adjacent thermal cells to capture distributed coupling interactions accurately.

If identified as necessary, mitigation techniques can include enlarging metal around hot spots, inserting thermal vias/plugs, and optimized floorplanning. Thermal analysis ensures designed stability and noise figure over the lifetime and use conditions of fielded systems.

10. Modeling and Mitigating Static Discharge Effects

As sensitive amplifying components, LNAs demand protection against damage from electrostatic discharge (ESD) events, which discharge thousands of volts through a chip in nanoseconds.

ESD analysis uses special models and non-linear simulations to predict maximum discharge current distributions and temperature rises. Zap tests of fabricated test structures help validate and improve modeling accuracy.

Based on results, protection measures such as power clamping diodes, RC filters, and grounded guard rings should be implemented to mitigate ESD risks and ensure the reliability and lifetime of LNAs.

LNA Optimization Approaches

With these myriad design considerations and tradeoffs involved, systematic LNA optimization is essential. Key optimization approaches include:

Multi-Objective Optimization

Formalizing the most critical performance attributes and employing multi-objective optimization algorithms helps automate optimizing component values and topology against multiple competing goals. Common focuses are minimizing noise figure, maximizing gain, and input match, within stability and power constraints.

Load Pull Analysis

Systematically varying impedance at the output tunes load lines presented to the active devices. The impacts on gain, stability, noise figure, and nonlinearity can be simulated pre-fabrication. Optimal load impedances and fundamental limitations become visible.

Automated Circuit Synthesis

Given basic performance goals and device library components, automated circuit generation tools can design, simulate, and optimize matching networks and biasing. This quickens the design process and provides good starting points for further manual optimization.

Combined judiciously, these approaches facilitate thorough exploration of the topology and parameter space to converge on high performance LNAs tailored for the target application.

LNA Topology Options

Many circuit topologies have been applied for LNA designs, with their own advantages and disadvantages. A brief overview of common options:

Common-Source (CS) Topology

The basic common-source architecture uses an input matching network feeding into the gate of a CS amplifier stage. Key features are simplicity and low component count. It provides moderate gain and noise figure. Drawbacks are potential stability challenges and higher distortion.

Common-Gate (CG) Topology

This architecture uses a CG input stage combining very low noise with broader band input match. The input impedance is resistive, simplifying matching. The topology enables excellent noise performance but has lower gain, requires higher bias power, and has potential stability issues.

Cascode Topology

Cascoding a CG input device with a CS or other configuration boosts the output impedance, isolation, and reverse isolation. This enhancement comes at the cost of higher bias power and noise figure. Additional gain stages may be added as well. Cascode LNAs provide very high stability and are popular for wireless infrastructure applications.