UseRogue.com的动态

Introducing a New Feature: Compare Assignees! If you’ve ever wondered how the patent strategies of two companies differ (for example, Intel vs. Micron), then the new Compare Assignees Tool will interest you. It summarizes the most critical Patent Title keywords used by the two companies, which helps to tell you where each company is heading (on their own), and highlights how their approach differs. https://lnkd.in/deBhxMTh #IDiyasNewFeature,?#CompareAssignees,?#CPCCodes,?#features,?#patents ,?#TitleKeywords,?#uspto Intel Corporation Micron Technology #companies

Industry leaders in chip design are always looking to cut costs on post silicon debug time. Post silicon debug is still evolving, with not so perfect solution for many issues; My commitment is to dedicate rest of my career/use my two and half decades of experience to develop debug design/to automate the pre-SI design/integration flows to help cut down on post-SI debug time.

While acknowledging that competitors may possess more extensive engineering teams or greater R&D investments, Lisa Su, CEO of AMD, emphasizes a crucial advantage: freedom. Within AMD, there exists a unique liberty to innovate, unbound by conventional constraints or bureaucratic hurdles. #eventprofs #traininganddevelopment #masterclass #innovation #creativity #keynotespeaker #alexanderblass

At a Staff meeting today, one of my team members asked how can one stay motivated during troubled times at Intel. It was a very relevant question. Here are 5 things you can do: 1. Approach work with discipline & not with motivation. Motivation can ebb and flow with what happens around you. But discipline is constant and not a choice. Time bound the task. 2. Add new, relevant arrows (skills) to your quiver. (If you are circuit designer, learn RTL verification or learn Post Silicon Debug) 3. Fill the dopamine bucket (Go for run, lift weights, do not eat food that is not naturally occurring, early to bed and rise, spend time with family, soak in the morning sunlight) 4. Never have more than 10% of your savings in one company's stock (learnt this the hard way) 5. Resolve to let go that which you cannot control. If you have been in a company that was in a similar situation as Intel is today, I would love to get your feedback on how you navigated that situation Cheers!

?? Day 13: 4-bit Comparator ?? #100daysofRTL Continuing my 100 Days of RTL Challenge, today I focused on designing a 4-bit Comparator! ?? 4-bit Comparator: A digital circuit that compares two 4-bit binary numbers and determines their equality, and which number is greater or smaller. It outputs three signals indicating whether one number is greater than, equal to, or less than the other. ?? Implementation: Utilizing smaller 2-bit comparators as building blocks, I created a hierarchical design to compare the most significant and least significant bits separately and then combine the results for the final comparison. Excited to share more insights and designs as I progress through this challenge! ???? #100DaysOfRTL #DigitalDesign #Verilog #FPGA #HardwareDesign #Engineering

For those who are curious what we mean by #advancedpackaging in the context of #foundry, listen to this interview between EE Times Nitin Dahad and Intel Foundry's Mark Gardner. Mark does an excellent job breaking down what it is and why it matters - and importantly why Intel's approach is a winner. Great 10 minute conversation. Have a listen.

?? Dive Deep into ASIC Synthesis ?? Curious about the backbone of the ASIC design flow? I've covered the critical stages of synthesis in my latest blog post on ChipWorld! From translating RTL code into gate-level representations to optimizing design for speed, power, and area, synthesis is where the magic happens! ? ?? In this article, you’ll learn about: Key transformations during synthesis Tools and strategies for achieving optimized designs Best practices for smooth transitions from RTL to gate-level Whether you're an experienced ASIC designer or just exploring the field, this post is packed with insights to strengthen your understanding of synthesis in the ASIC workflow. ?? Read it here: https://lnkd.in/d-548MWB ?? I’d love to hear your thoughts! What challenges have you faced in the synthesis process? Let's discuss! #ASICDesign #Synthesis #ChipDesign #VLSI #Semiconductor #Engineering #TechInsights

The Intel Foundry launch last month brought around 1,200 people together in San Jose, California, to demonstrate the power of an ecosystem working together to deliver silicon for the AI era. In this conversation Mark Gardner articulates why advanced packaging is important and how Intel's new 'ASAT' service will help customers deliver optimized packaging for the evolving heterogenous, multi-die and chiplet based systems needed to enable high performance AI compute. In addition, partners applauded the wider ecosystem approach by Intel Corporation - you can read more about this in my full story in EE Times | Electronic Engineering Times here, https://lnkd.in/eRm6-JVc , which includes a video interview with Aart de Geus of Synopsys Inc. #semiconductormanufacturing #foundry #chipsact #aicomputing #ai #foundry