NEO Semiconductor的动态

A number of readers of yesterday's Intel 18A yield post https://lnkd.in/gu4meEjV pointed out the use of the Bose-Einstein yield model Y=1/(1+AD0)^n. It is shown for a D0=0.05/cm2, A=1cm2 die size below. There are quite a few critical layers at advanced nodes, such as multipatterning with EUV. The more of these layers (higher n), the lower the expected yield. Thanks Pratyush Kamal and Qiang F. for referring to this model!

As the chiplet ecosystem rapidly expands, effective simulation and interoperability testing of UCIe IP is crucial. Read the white paper and discover how Intel and Cadence drive robust solutions in chiplet-based designs. https://ow.ly/utSR50TrwpU

Great piece by Kevin Mak from TechInsights on the Sheba Sharp-7 Autofocus Automotive Camera, demonstrated in a real-time benchmark test at AutoSens Europe Oct. 8-10, 2024 with DXOMARK. ABOUT THE SHARP-7: As the automotive sensor market continues to trend towards higher resolution sensors, the problem of lens thermal expansion becomes increasingly pronounced due to the sensors’ smaller pixel size. This is because smaller pixels require more precise alignment of the optics to ensure that light is accurately focused on each pixel, and any misalignment due to thermal expansion or contraction can lead to blurring or distortion – problematic for any camera and especially for automotive due to the extended temperature range. Solving for ultra-precise alignment becomes not just a “nice to have” – but absolutely critical. EVAL KIT: To test the Sharp-7 in your own labs: https://lnkd.in/g4NXbepi #ADAS #AutomotiveCamera #AutoSens Faez Ba-Tis Ridha Ben Mrad Laurent Chanas Fabien Montagné

"Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor market. This Tech Talk article talks about the evolutions of LPDDR DRAMs leading to the latest published standard of LPDDR5/5X. " Read the Cadence Tech Talk article now https://ow.ly/6Ljc50Sxyyr

Single Vs. Multi-Patterning Advancements For EUV https://lnkd.in/eK7cDx5U EUV patterning has come a long way in the past five years, but old challenges resurface with high-NA EUV. By Gregory Haley. #semiconductor #EUVlithography #HighNAEUV #singlepatterning Chris Mack Fractilia Kevin Lucas Synopsys Inc ASML Harry Levinson Leo Pang D2S, Inc. Boyd F. Tignis #3nm #multipatterning

Dr. Hany F. from Intelligent Solution tells us about the new trends in the semiconductor industry: chiplets. ???? Talking about chiplets connected with passive interconnects and supporting high data rates, this includes high-frequency effects. For this, understanding full 3D wave propagation is a must. Dr. Hany explains how CST Studio Suite serves his needs.

Meet Frederic Leens and I to see how you can boost your SoC debug.

As the chiplet ecosystem rapidly expands, effective simulation and interoperability testing of UCIe IP is crucial. Read the white paper and discover how Intel and Cadence drive robust solutions in chiplet-based designs. https://ow.ly/yljt50SZo9E

?? Unearth the next wave of semiconductor innovation! Chat with our very own Sergio Timpretti and NXP Semiconductors' Justin Mortimer about the game-changing MCX MCU series and the future of the industry. Get the inside scoop here ?? https://bit.ly/3x4Wu0V #NXP #MCX #MCU #Technology #Microcontrollers

As the chiplet ecosystem rapidly expands, effective simulation and interoperability testing of UCIe IP is crucial. Read the white paper and discover how Intel and Cadence drive robust solutions in chiplet-based designs. https://ow.ly/vZhC50SYV6Q