In the late 90s and early 2000s, the data center server market shifted from sealed boxes from single vendors to an ecosystem of interoperable hardware and software. The same them occurred in telco. The same is now occurring in switches with SONiC and chips like Teralynx 10, says Nick Kucharewski of Marvell Technology at #OCP 24. Tearalynx 10, he added, "is being deployed in global cloud networks as we speak." "The decision to buy 1000s of systems from a vendor becomes an operational decision not an architectural decision."
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PCIe at OCP? You know me. The first public showing of the PCIe Gen 6 retimer from Marvell Technology. Think of PCIe retimers as turbochargers: they clean and amplify signals between CPUs and GPUs. Without them, signals would start to get corrupted two inches into their voyage. (The copper components also combine SerDes from the optical world.) 650 Group predicts 75% of AI and cloud servers will have PCIe retimers on the board and there might be two per GPU.
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It’s the final day of OCP Global Summit 2024, but there’s still time to stop by the Marvell booth (B1)! Come explore our demos and see how we’re driving the future of AI, cloud and data infrastructure. Don’t miss out on the chance to connect with our experts and discover the latest innovations from Marvell. See you at Booth B1!
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Like the Beatles, the Marvell Technology Nova 2, the world's first 1.6T optical DSP with 200G lanes per lambda or channel, made its debut in a grotty basement in Germany (the Frankfurt convention center) but the fans really went bonkers when it landed in the States. It's pure DSP mania at #OCP 24. In the near future: linking cutting edge AI clusters. Whamda Lambda Ding Dong!
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Global business and marketing executive passionate about advancing society with technology, product and business innovations
Thank you to the Open Compute Project Foundation for the opportunity to be on yesterday's OCP Summit keynote panel with Chris Petersen of Astera Labs, Taeksang Song of Samsung Electronics and James Kelly of #OCP. I enjoyed discussing some of the key interconnect and memory challenge areas that we are working to address and must continue to collaborate as an industry in order to scale AI clusters. For those who missed it, you can catch a replay here: https://lnkd.in/g4J-TdMb Marvell Technology is focused on AI for AI, accelerated infrastructure for artificial intelligence, and we're collaborating with industry leaders to help scale it with the industry's most comprehensive connectivity and custom compute portfolio. Contact us to see how we can help scale your infrastructure for the AI era.
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Join Marvell Technology today and tomorrow at IEEE Ethernet & IP @ Automotive Technology Day in Detroit!
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Join Marvell at OCP Global Summit 2024 for "Memory Wall Mitigation and Acceleration of AI Workloads, and In-Memory Databases Using CXL Near Memory Compute Accelerator," presented by Gaurav Agarwal, Senior Director Engineering. In this session, explore how CXL-based Near Memory Compute (NMC) architectures are optimized for hyperscale environments to meet the demands of processing vast amounts of data. DETAILS Date: Thursday, October 17 Time: 12:30 p.m. PT Location: Concourse Level – 210BF Make sure to visit our booth (B1) for live demos! See the full schedule here: https://mrvl.co/3zDb6WL Open Compute Project Foundation
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Feast your eyes people: it's the 3nm PCIe Gen 7 SerDes from Marvell Technology at OCP 24. Why is it a big deal? --Capable of transferring 128GB per second between GPUs, XPUs, CPUs and other chips, it will help keep up with the speed and data movement demands of AI. --128 is 4x what the best PCIe Gen 5 devices out now do. -- There's a distance angle. At 128GB/s chips would have to be inches apart to communicate. multiprocessing systems would be impossible. Putting this SerDes in a PCIe retimer, a new category of chips, would greatly expand the distance. -- Call it Coptical.The PAM4 SerDes here was originally developed for optical. Think of this as a hybrid of copper and optical tech. -- 3nm means lower power. Chips on this process are just ekeing out. --The SerDes is the chip. The eye diagram shows strong performance and we'd like to than Textronix for the help in testing.
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Join Marvell at OCP Global Summit 2024 for "Realizing Composable Infrastructure Through DPUs," presented by Satananda Burla, Senior Principal Engineer. In this session, discover how composable infrastructure separates resources and hardware, making them accessible from anywhere in the data center. Learn how Data Processing Units (DPUs) enable cloud service providers to combine resources like compute, DDR, storage, and networks on demand to efficiently run workloads. DETAILS Date: Thursday, October 17 Time: 8:30 a.m. PT Location: Concourse Level – 210CG See the full lineup of Marvell presentations at the event and don’t forget to stop by the booth (B1) to see live demos: https://mrvl.co/3zDb6WL Open Compute Project Foundation
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