Lightelligence的动态

Check out this highlight from our recent partnership with Arm at OCP, where Sue Hung F. and Sridhar Valluru engaged the audience with an insightful presentation on Alphawave Semi's new off-the-shelf I/O chiplet. This innovative #chiplet features UCIe die-to-die interconnect and supports Ethernet, PCIe, and CXL. Our diverse chiplet portfolio, combined with the ARM Neoverse compute chiplet and various memory chiplets, empowers the creation of high-performance systems that meet the evolving demands of AI/ML and data centers—ensuring scalability and future-proofing with next-gen silicon-proven IP. Watch the the full presentation here: https://lnkd.in/eAgchRwp? #AlphawaveSemi #ConnectivityIP #ConnectivitySolutions #Chiplets #AI #Connectivity #CustomSilicon #Silicon

?? iW-RainboW-G52M: Virtex UltraScale+ System on Module, a cutting-edge #SoM designed to redefine performance standards in #FPGA technology, featuring:? -Up to 3,780K Logic cells & 1,728K LUTs -Massive memory interface bandwidth with DDR4 -76 high-speed transceivers for unparalleled data throughput ? Ideal for compute-intensive applications across sectors like #datacenters, #radar, and #wiredcommunications. With a dual Arm Cortex-A72 processor and extensive connectivity options, this module ensures seamless integration and rapid deployment of next-gen technologies. ? AMD ? #iWaveGlobal #AMD #VirtexUltraScale #SystemOnModule #embeddedsystems

Got my hands on some old - Intel Xeon Phi 5110P 60-Core 1.053GHz Coprocessors. These older generation devices from DECOM'd data centers are exactly what I need for my experiments. #EfficientCoding #CompactMLforIOT #TINYMLforMicrodevices

In our latest video, Suanming Mou from NVIDIA shares valuable insights on optimizing unified representors with large-scale ports using DPDK. ?? Full DPDK APAC Summit presentation here: https://lnkd.in/g7vZUH2C? ?? Main points ?? : 1. Enhanced Efficiency: By disabling the represent match feature, all packets are dedicated to a single uplink representor port, drastically reducing memory and CPU overhead. 2. Optimized Packet Handling: Flow rules are set to copy source port ID information into packet metadata, allowing the hypervisor to identify the source port without polling multiple ports. 3. Significant Performance Gains: The optimization reduces memory usage from over 800MB to around 332MD and improves packet processing speed from 20 Mega PPS to 27.5 Mega PPS. Discover how these optimizations can revolutionize network performance. #DPDKSummit #DPDK #network #technology

At AI dominated #CES 2025, #NVIDIA unveiled the GeForce RTX 50 series with Blackwell architecture GPU, highlighting the growing importance of AI. The demand for high-speed data transmission is soaring, driven by the exponential increase in data generation. 800G optical transceivers offer a solution, providing lightning-fast speeds and reliability for data centers worldwide. They handle multimodal data and complement NVIDIA's GPUs, ensuring seamless transmission and superior signal quality. With high performance, reliability, compatibility, and low power consumption, ATOP 800G optical transceivers are ideal for modern data centers and AI applications . They help unlock the full potential of NVIDIA GPUs, making them the perfect partner for keeping pace with technological evolution.?

Computational fluid dynamics like never seen before, all on a single node. ?? From massive jet simulations to intricate raindrop dynamics, #IntelXeon 6 with P-cores redefine #HPC limits, supporting OpenCL and AVX-512 workloads with efficiency and speed. Visit Intel at #SC24 to watch real-time fluid dynamics simulations and learn how Intel Xeon 6 is powering the future of high performance computing. https://intel.ly/3ARbSjl #FluidDynamics

PCI Gen 6 is setting new standards for high-speed data transfer, bringing significant improvements in physical layer design. This whitepaper dives into the evolution of PCIe interconnects, exploring Gen6 Ordered Set Blocks, Flit Data Stream Mode, and the steps involved in Tx and Rx PHY Layer. Learn how these advancements enhance performance and reduce Bit Error Rate (BER). Get the full details in our whitepaper - https://lnkd.in/g3hXf3Kn #PCIeGen6 #DataTransfer #TechInnovation #PhysicalLayer #HighSpeedConnectivity #EngineeringExcellence #LogicFruitTech

Alphawave Semi is making waves at SC’24! We’re proud to showcase an industry first multi-protocol 1.6Tbps IO chiplet tile from our standard chiplet portfolio. See demo booth showcased below. Parts for die, packaged parts and boards are available today. In another booth, driving the next generation of supercompute, the standard chiplet portfolio also showcases the Arm Neoverse CSS-based CPU chiplet paired with Alphawave Semi's energy-efficient interfaces and Lessengers’ optics, delivering scalable performance for AI, HPC, and networking infrastructure. Co-packaged optics samples demonstrating advanced remote accelerator connectivity integration—helping reduce costs and power consumption for XPUs and PCIe switches, while our low-latency interfaces enhance memory expansion for both capacity and bandwidth. Also, don’t miss: Demo of our complete PCIe solution in collaboration with Keysight at the PCI-SIG booth. A low-latency, low-power solution for disaggregated CXL over copper with Amphenol in the CXL booth. Whether optical or electrical, Alphawave Semi has the cutting-edge solutions to power your AI and ML needs. Come see the Wavemakers! #SC24 #PCIe #CXL #Chiplets #UCIe #Optics #Supercomputing

Alphawave Reveals Multiprotocol I/O Chiplet Tapeout, Collabs with Arm, Samsung. Designed specifically for HPC and AI infrastructure, the chiplet integrates multiple communication protocols, including PCIe, CXL, and Ethernet, into a single silicon device to enhance data throughput and connectivity in demanding computational environments. To achieve this, the chiplet leverages Alphawave’s advanced SerDes technology, which provides high-speed serial data transmission to allow the chiplet to support data rates up to 112 Gbps. Such high-speed capability significantly reduces latency and increases the overall performance of HPC and AI workloads, enabling rapid data exchange between processors, accelerators, and memory subsystems - https://lnkd.in/gbV5Z9pB

Explore the enhanced features of OPENEDGES' DDR memory PHY: ?? Multiple FSPs for optimal performance ?? Supports multiple ranks for versatility ?? Fully independent channels (operating frequency, power state) for customized control ?? Firmware-based training and production test features for seamless integration ?? Configurable number of CA lanes for adaptability ? Flexible floorplan and signal ordering for tailored design solutions ?? Visit https://lnkd.in/diNaBBih for more info. #OPENEDGES #DDRPHY #TheSixSemi #TSS #PHY