Silogy

Chip teams spend up to 70% of their time on design verification. And with a widening gap in productivity between design and verification, the problem is only growing. The reason? Verification engineers are stuck doing repetitive tasks, like tracking down log files, rerunning failing tests, updating Excel-based test plans, and manually combing through waveforms. And new tooling hasn't come in to ameliorate that situation. That is, until we at Silogy decided to tackle the problem ourselves. Our AI-powered tools, such as Viv, our virtual verification engineer, help verification engineers root-cause test failures 10x faster. This means verification engineers and chip designers alike can spend less time on the rote tasks of verification and more time getting results. If design verification is a problem at your company, I'd love to talk with you. Shoot me a message or just book a time with us. Link below.

All throughout YC, we tried to stay out of the AI-hype game. We even raised without AI being a core part of our pitch. But it's become increasingly clear that LLMs are going to transform the landscape of digital circuit design. That's why we at Silogy are building Viv, the world's first virtual verification engineer. Design verification takes up to 70% of development time when designing chips. But the process is slow and repetitive. Viv solves this by automatically debugging failing test regressions by reading log files, inspecting code, and stepping through waveform files. We've already seen Viv tease out subtle RTL bugs from code that had been checked in weeks ago. If you're involved in chip design and want to see Viv in action, shoot me a message.

Today our founding engineer James C. open-sourced our test runner library Smelt. Smelt is a simple and extensible task runner optimized for chip development workflows which makes it easy to programmatically define arbitrarily many test variants, run those tests in parallel, and analyze their results. If you work in chip development, we would love your feedback. Feel free to comment either here or in our Show HN post linked below. https://lnkd.in/eVStaFzq https://lnkd.in/e_wKjqsq

I will be at #DAC61 this year representing Silogy. If you want to chat please reach out! Especially about design verification, AI, or both.

If only there were a Y Combinator-backed company of big dreamers looking to tackle this immense and under-appreciated problem... maybe using AI? https://lnkd.in/eEWWqgxB