Rise Design Automation

Great to see the smiling faces in interview with Badru Agarwala and Sanjay Gangal on EDA Cafe talking about the Generative AI solution for semiconductor design from Rise Design Automation. Check it out and let us know what you think. https://lnkd.in/gWSBK86j

We are seeing that Generative AI+Raised Abstraction with a human-in-the loop is working very well to generate quality RTL. Check out Bernards article from our discussions at DVCon. https://lnkd.in/g3ZTi4_Q

Having a great "first since out of stealth-mode" DVCon U.S. The attendance this year seems higher than usual and we have had some great conversations at our booth and catching up with old friends. Most popular discussions have been our Gen AI capabilities, how to verify at high-level and what SystemVerilog looks like to design at high-level. Everyone is liking (and surprised) that we are doing a real demo at a show!! Last day today so hope to see you there.

Really looking forward to DVCon U.S. next week. It is our first conference since coming out of stealth mode and we are really looking forward to seeing and talking with old friends and making new ones. Please come visit us at Booth #121. See you there! #DVCon_US #EDA #dvcon #Rise #AI

First big interview from Badru on Rise Design Automation with Danniel Nenni from SemiWiki. Topics ranged from how generative AI and raised abstraction can work together today to what high-level means in a language like SystemVerilog. An interesting read.

A really insightful interview by Daniel Nenni from SemiWiki with Badru Agarwala CEO of Rise Design Automation. They cover a wide range of topics from the RDA mission to how generative AI can be deployed today for semiconductor design and verification. Read the full interview here https://lnkd.in/gY6NT7Zb

?????? ???????????????????? ???? ???????? ?????? ???????????? ????????-?????????????? ?????? ?????????????? ?????? ???? ?????????????????????????It can if you raise the abstraction beyond RTL!? ?? Watch our free On-Demand technical webinar that demonstrates how Rise tools uniquely combine high-level design (using SystemVerilog, C++ or SystemC) with Generative AI to enable the fastest path to the QoR in RTL you need in dramatically less time. ?? Register here: https://lnkd.in/gkbZxd9n

Thanks so much to Brian for a thought provoking article on startups in EDA! We need more of them, so how do we as an industry foster more startups and innovation. At Rise we have many, many years of experience, and know the industry well, but would be more interested to hear what you all think! EDA is indeed an important catalyst for the multi-billion dollar semiconductor industry, but how do we accelerate much needed innovation, and frankly, more revolutionary thinking? https://lnkd.in/g4CW2fpu

Wishing everyone a Happy Holiday season and a Prosperous New Year from the entire Rise team!

???????? ???? ?? ?????????? ???????? ???? ?????? ???????? #????-?????????????? ?????????????? generating a design in high-level SystemVerilog that is optimized for synthesis. To see the full presentation of how it works and demonstration ???????? ?????? ??-???????? ??????????????:??? "???????? ?????????????? ???? ??????: ?????????????????? ???????????????????? ???? ?????? ???????? ???????????????? ?????? ??????????????????" ?? December 12th, 9amPST ?? Save your spot today: https://lnkd.in/g3JMr4ag