IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM)

The IEEE International Symposium on Field-Programmable Custom Computing Machines is the original and premier forum for new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware. Over the past two decades, FCCM has been the place to present papers on architectures, tools, and programming models for field-programmable custom computing machines as well as applications that use such systems. This year FCCM seeks to embrace its role as the venue where “firsts” are presented by encouraging submissions describing new forward-thinking research on emerging technologies with in-field reconfiguration capabilities for the upcoming post-Moore’s Law era. Submission Link: https://lnkd.in/efBX3pdH Call for Paper Details:?https://lnkd.in/dTVRkDGg Topics of interest: Custom Computing and Reconfigurable Architectures: Heterogeneous and mixed signal digital/analog field customizable accelerators Neuromorphic emulation and accelerators Memory centric computing architectures Overlays, coarse grained reconfigurable architectures Clusters, data centers, and large systems IoT and Embedded SoC, MPSoC architectures with reconfigurable devices Security enhancements for reconfigurable computing Customizable soft processor systems Abstractions, Programming Models, and Tools: Use of Large Language Models (LLMs) for FPGA design Domain-specific languages, frameworks, and open-source hw/sw synthesis/compilation tools Design tools, instrumentation, debug for designer productivity High-level synthesis Software-defined-systems (e.g. radio, networks, frameworks for new domains) CAD tools, abstractions and languages for mixed analog/digital fabrics Run Time Reconfiguration: Run-time management and scheduling of reconfigurable hardware System resilience/fault tolerance for reconfigurable hardware Evolvable, adaptable, approximate, or autonomous reconfigurable computing systems Security assessment and enhancement of run-time reconfiguration Applications: Evaluations and analysis on custom computing architectures with GPUs, NPUs, or DSPs Post Quantum Cryptography, Quantum control and emulation Safety critical, reliable and high assurance Security detection and prevention, and Side Channel analysis and Attack Digital twin, modeling, and acceleration Submissions can be made for any of the two paper types: Traditional technical long papers that introduce and evaluate new technologies. These papers must have strong empirical results and address significant challenges of the corresponding problem.?Page length is 8 pgs (excluding references). Short papers intended for new projects, early results, late breaking, and work that can be presented concisely.?Page length is 4 pgs (excluding references). Due Dates: Abstracts Due (All Papers) January 10, 2025 Submissions Due (All Papers) January 17, 2025 David Andrews, Andrew Schmidt, Lana Josipovi?, Cong (Callie) Hao, Peipei Zhou

The IEEE International Symposium on Field-Programmable Custom Computing Machines is the original and premier forum for new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware. Over the past two decades, FCCM has been the place to present papers on architectures, tools, and programming models for field-programmable custom computing machines as well as applications that use such systems. This year FCCM seeks to embrace its role as the venue where “firsts” are presented by encouraging submissions describing new forward-thinking research on emerging technologies with in-field reconfiguration capabilities for the upcoming post-Moore’s Law era. Submission Link: https://lnkd.in/efBX3pdH Topics of interest: Custom Computing and Reconfigurable Architectures: Heterogeneous and mixed signal digital/analog field customizable accelerators Neuromorphic emulation and accelerators Memory centric computing architectures Overlays, coarse grained reconfigurable architectures Clusters, data centers, and large systems IoT and Embedded SoC, MPSoC architectures with reconfigurable devices Security enhancements for reconfigurable computing Customizable soft processor systems Abstractions, Programming Models, and Tools: Use of Large Language Models (LLMs) for FPGA design Domain-specific languages, frameworks, and open-source hw/sw synthesis/compilation tools Design tools, instrumentation, debug for designer productivity High-level synthesis Software-defined-systems (e.g. radio, networks, frameworks for new domains) CAD tools, abstractions and languages for mixed analog/digital fabrics Run Time Reconfiguration: Run-time management and scheduling of reconfigurable hardware System resilience/fault tolerance for reconfigurable hardware Evolvable, adaptable, approximate, or autonomous reconfigurable computing systems Security assessment and enhancement of run-time reconfiguration Applications: Evaluations and analysis on custom computing architectures with GPUs, NPUs, or DSPs Post Quantum Cryptography, Quantum control and emulation Safety critical, reliable and high assurance Security detection and prevention, and Side Channel analysis and Attack Digital twin, modeling, and acceleration Submissions can be made for any of the two paper types: Traditional technical long papers that introduce and evaluate new technologies. These papers must have strong empirical results and address significant challenges of the corresponding problem.?Page length is 8 pgs (excluding references). Short papers intended for new projects, early results, late breaking, and work that can be presented concisely.?Page length is 4 pgs (excluding references). Due Dates: Abstracts Due (All Papers) January 10, 2025 Submissions Due (All Papers) January 17, 2025 Rebuttal Period February 10 - 14, 2025 Notification of Acceptance (All Papers) March 10, 2025 David Andrews, Andrew Schmidt, Peipei Zhou

The IEEE International Symposium on Field-Programmable Custom Computing Machines is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware. Over the past two decades, FCCM has been the place to present papers on architectures, tools, and programming models for field-programmable custom computing machines as well as applications that use such systems. This year FCCM seeks to embrace its role as the venue where “firsts” are presented by encouraging submissions describing new forward-thinking research on emerging technologies with in-field reconfiguration capabilities for the upcoming post-Moore’s Law era. Topics of interest include but are not limited to: Custom Computing and Reconfigurable Architectures: Heterogeneous and mixed signal digital/analog field customizable accelerators Neuromorphic emulation and accelerators Memory centric computing architectures Overlays, coarse grained reconfigurable architectures Clusters, data centers, and large systems IoT and Embedded SoC, MPSoC architectures with reconfigurable devices Security enhancements for reconfigurable computing Customizable soft processor systems Abstractions, Programming Models, and Tools: Use of Large Language Models (LLMs) for FPGA design Domain-specific languages, frameworks, and open-source hw/sw synthesis/compilation tools Design tools, instrumentation, debug for designer productivity High-level synthesis Software-defined-systems (e.g. radio, networks, frameworks for new domains) CAD tools, abstractions and languages for mixed analog/digital fabrics Run Time Reconfiguration: Run-time management and scheduling of reconfigurable hardware System resilience/fault tolerance for reconfigurable hardware Evolvable, adaptable, approximate, or autonomous reconfigurable computing systems Security assessment and enhancement of run-time reconfiguration Applications: Evaluations and analysis on custom computing architectures with GPUs, NPUs, or DSPs Post Quantum Cryptography, Quantum control and emulation Safety critical, reliable and high assurance Security detection and prevention, and Side Channel analysis and Attack Digital twin, modeling, and acceleration Submissions can be made for any of the two paper types: Traditional technical long papers that introduce and evaluate new technologies. These papers must have strong empirical results and address significant challenges of the corresponding problem.?Page length is 8 pages (excluding references). Short papers intended for new projects, early results, late breaking, and work that can be presented concisely.?Page length is 4 pages (excluding references). Due Dates: Abstracts Due (All Papers) January 10, 2025 Submissions Due (All Papers) January 17, 2025 Rebuttal Period February 10 - 14, 2025 Notification of Acceptance (All Papers) March 10, 2025 David Andrews, Andrew Schmidt, Peipei Zhou

The IEEE International Symposium on Field-Programmable Custom Computing Machines is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware. Over the past two decades, FCCM has been the place to present papers on architectures, tools, and programming models for field-programmable custom computing machines as well as applications that use such systems. This year FCCM seeks to embrace its role as the venue where “firsts” are presented by encouraging submissions describing new forward-thinking research on emerging technologies with in-field reconfiguration capabilities for the upcoming post-Moore’s Law era. ? Topics of interest include but are not limited to: Custom Computing and Reconfigurable Architectures: Heterogeneous and mixed signal digital/analog field customizable accelerators Neuromorphic emulation and accelerators Memory centric computing architectures? Overlays, coarse grained reconfigurable architectures Clusters, data centers, and large systems IoT and Embedded SoC, MPSoC architectures with reconfigurable devices? Security enhancements for reconfigurable computing Customizable soft processor systems Abstractions, Programming Models, and Tools: Use of Large Language Models (LLMs) for FPGA design? Domain-specific languages, frameworks, and open-source hw/sw synthesis/compilation tools Design tools, instrumentation, debug for designer productivity High-level synthesis? Software-defined-systems (e.g. radio, networks, frameworks for new domains) CAD tools, abstractions and languages for mixed analog/digital fabrics Run Time Reconfiguration: Run-time management and scheduling of reconfigurable hardware System resilience/fault tolerance for reconfigurable hardware Evolvable, adaptable, approximate, or autonomous reconfigurable computing systems Security assessment and enhancement of run-time reconfiguration Applications: Evaluations and analysis on custom computing architectures with GPUs, NPUs, or DSPs Post Quantum Cryptography, Quantum control and emulation Safety critical, reliable and high assurance? Security detection and prevention, and Side Channel analysis and Attack?? Digital twin, modeling, and acceleration Submissions can be made for any of the two paper types: Traditional technical long papers that introduce and evaluate new technologies. These papers must have strong empirical results and address significant challenges of the corresponding problem.? Page length is 8 pages (excluding references). Short papers intended for new projects, early results, late breaking, and work that can be presented concisely.? Page length is 4 pages (excluding references). Due Dates: Abstracts Due (All Papers) January 10, 2025 Submissions Due (All Papers) January 17, 2025 Rebuttal Period February 10 - 14, 2025 Notification of Acceptance (All Papers) March 10, 2025 David Andrews, Andrew Schmidt

The IEEE International Symposium on Field-Programmable Custom Computing Machines is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware. Over the past two decades, FCCM has been the place to present papers on architectures, tools, and programming models for field-programmable custom computing machines as well as applications that use such systems. This year FCCM seeks to embrace its role as the venue where “firsts” are presented by encouraging submissions describing new forward-thinking research on emerging technologies with in-field reconfiguration capabilities for the upcoming post-Moore’s Law era. ? Topics of interest include but are not limited to: Custom Computing and Reconfigurable Architectures: Heterogeneous and mixed signal digital/analog field customizable accelerators Neuromorphic emulation and accelerators Memory centric computing architectures? Overlays, coarse grained reconfigurable architectures Clusters, data centers, and large systems IoT and Embedded SoC, MPSoC architectures with reconfigurable devices? Security enhancements for reconfigurable computing Customizable soft processor systems Abstractions, Programming Models, and Tools: Use of Large Language Models (LLMs) for FPGA design? Domain-specific languages, frameworks, and open-source hw/sw synthesis/compilation tools Design tools, instrumentation, debug for designer productivity High-level synthesis? Software-defined-systems (e.g. radio, networks, frameworks for new domains) CAD tools, abstractions and languages for mixed analog/digital fabrics Run Time Reconfiguration: Run-time management and scheduling of reconfigurable hardware System resilience/fault tolerance for reconfigurable hardware Evolvable, adaptable, approximate, or autonomous reconfigurable computing systems Security assessment and enhancement of run-time reconfiguration Applications: Evaluations and analysis on custom computing architectures with GPUs, NPUs, or DSPs Post Quantum Cryptography, Quantum control and emulation Safety critical, reliable and high assurance? Security detection and prevention, and Side Channel analysis and Attack?? Digital twin, modeling, and acceleration Submissions can be made for any of the two paper types: Traditional technical long papers that introduce and evaluate new technologies. These papers must have strong empirical results and address significant challenges of the corresponding problem.? Page length is 8 pages (excluding references). Short papers intended for new projects, early results, late breaking, and work that can be presented concisely.? Page length is 4 pages (excluding references). Due Dates: Abstracts Due (All Papers) January 10, 2025 Submissions Due (All Papers) January 17, 2025 Rebuttal Period February 10 - 14, 2025 Notification of Acceptance (All Papers) March 10, 2025 David Andrews, Andrew Schmidt

I cannot believe it has already been 2 weeks since I attended the IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM) in Orlando, FL, and presented our paper, "FINESSD: Near-Storage Feature Selection with Mutual Information for Resource-Limited FPGAs." You can find the paper here: https://lnkd.in/gXwKs9HX , where you can see how to harness near-storage FPGAs to filter larger-than-memory datasets directly where the data lie and gain speed-up and energy savings. Meeting so many talented, brilliant people and discussing the latest developments on FPGAs (and more) was a fantastic experience! In the picture: I am discussing possible future directions for LightningSim with Rishov Sarkar and Petros Toupas.

I am happy to share that last week I presented our paper titled "HardCilk: Cilk-like Task Parallelism for FPGAs" in the 32nd IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM) 2024. **The paper was a best paper candidate.** I would like to thank the organizing committee for the great organization and the nice time in Orlando. I would also like to thank the co-authors Canberk S?nmez, Cemalettin Cem Belentepe, and our supervisor Prof. Paolo Ienne Main Contributions: 1. HardCilk: An open-source architectural generator for task parallel accelerators 2. Architectural components are fully virtualized 3. Designs are highly tolerant to memory latency 4. Support for full spatial configuration of tasks 5. Support for Decouple Access Execute * You can watch the conference presentation to get the gist behind the paper, link: https://lnkd.in/eE-hH6Yi * Read how we automatically generate task parallel accelerators for FPGAs in our paper, link: https://lnkd.in/ei5XHpCw * Use our open-source tool now to create your customized task parallel accelerators, repo Link: https://lnkd.in/e2Uat9gB Canberk S?nmez and I were lucky to witness a SpaceX Falcon 9 launch at Kennedy Space Center after the presentation, you can see how amazed we were by the smile on our faces below.

I'm really glad to have a chance to attend the IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM) in Orlando last week and display our work "BitSys: Bitwise Systolic Array Architecture for Multi-precision Quantized Hardware Accelerators" as one poster there. Salim Ullah , Akash Kumar , and I explored a novel systolic array architecture of runtime reconfigurable multi-precision multi-channel multipier supporting high clock frequency. It's my first time to be in US and I'm really happy to meet so many talent people and brilliant works. I hope we can keep in touch and have more collaboration and discussion in the further.

In the last week I've been busy! I graduated with my B.S. in Electrical Engineering after 4 years and will be coming back to UF for another year to earn my masters degree in electrical and computer engineering. I was invited to attend the IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM) by Dr. Christophe Bobda and got to hear about cutting edge FPGA research developments from the likes of Dr. Jason Cong. Finally, I drove across the country to San Jose California to work as a Digital Design Engineer Intern at Astera Labs for the summer. I'm super excited to explore the bay area and learn from the amazing people at Astera. Thank you to all the professors and peers who helped me throughout the last four years in becoming the engineer I am today!