Efabless Corporation

Excited to share my first #analog #VLSI chip design, working, on #TinyTapeout 6: A simple 24-bit(ish)-colour analog VGA test pattern generator. This was my 7th tapeout (back in April 2024) but my first mixed-signal design & custom layout; rough, but I'm delighted that it works better than expected! See my detailed testing write-up here: https://algo.org/tt06 -- and watch my segment on the TT06 Bring-Up Party video: https://lnkd.in/gM_yDADJ Thanks Matt Venn: you started me on this journey and I learned to lay out, verify, and simulate my design from your Zero to ASIC Analog Course: https://lnkd.in/gKxCtD2F Thanks Efabless Corporation for the silicon fabrication, Tiny Tapeout sponsorship, and #opensource PDK/toolchain that make this all possible. Thanks Sylvain Munaut for invaluable help with the external buffer design that really let this thing out of the box! Stay tuned for an update in TT08, and hopefully also TT10. #ChipDesign #sky130 #openASICs #ASIC #FPGA #Efabless

Made a leap closer to see my RTL designs transformed into a physical chip, today I am excited to share that I have achieved a milestone, RTL-to-GSDII. I successfully taped out a high-performance SPI-based Arithmetic Logic Unit, incorporating industry-grade operations such as: ? Wallace Tree Multipliers ? Brent-Kung Adders ? LUT Approximation Dividers ? Generic GCLA Adders ? Bitwise Operation logic The design uses the SPI protocol for communication between the ALU and a host device hoping it may be used as a math coprocessor at some point. Key highlights of this project include: ? RTL Design & Verification: developing the RTL architecture and thoroughly verified the design using Cocotb and synthesized using Verilator and Yosys. ? Emulation Verification: Emulated RTL on a FPGA (Altera Cyclone V) for timing and functional verification. ? Tape-Out/GSDII: Generating RTL netlists to GSDII format using Skywater 130nm PDK, bringing this work a step closer to physical realization (lithography at least). Huge thanks to the folks at?Efabless Corporation?for the amazing tooling and resources they provide for design sign-offs rule checks and RTL-to-GSDII flow. Up next, I will be trying to figure out the packaging side of this chip!

Open source is not just for foundation models... Last week Joseph and I presented our "Win Story" to AWS' GTM org where a global software company adopted Amazon Managed Prometheus for their observability needs. It's exciting to see how open source platforms provide a cost-effective alternative for builders working on observability, generative AI (DeepSeek AI),and even semiconductor chip design (quick plug for Mike's Efabless Corporation). This engagement has been a great learning experience and a team effort. AWS' account, product, and technical specialist teams really exhibit ownership and customer obsession. Excited to help our customers leverage AWS' managed open source solutions to ensure their businesses provide a world class digital experience. Amazon Web Services (AWS)

"+6.7V, -3.8V, and we're done!" I really wanted to use flash memory on Tiny Tapeout, but there was a "tiny" problem - no open source flash IP for sky130. Armed with exactly zero analog design experience, I took a deep dive into the PDK docs, which confidently promised: "Give us +6.7V and -3.8V, and we'll take you to the non-volatile memory paradise!". "No prob, I'll pump some electrons", I said, and spent the next three days learning about charge pumps and designing one, which I proudly taped out on Tiny Tapeout 6. It actually worked! ?? https://lnkd.in/d6tUjAkC Little did I know how far I was from done. Generating weird voltages? "easy". Controlling those voltages? That's a whole different story. I fought body diode leaks, sneaky negative nwells bleeding into the psubstrate. Every time I thought I was done, the voltage found another way to escape or threatened to break down the gate oxide; huge shoutout to Sylvain Munaut for catching those! I'm still pretty skeptical this is going to work, but at least ngspice is optimistic. We'll submit it on Tiny Tapeout 10 and find out in a few months once the silicon comes back. Big kudos to Aidan Medcalf who volunteered to do the physical layout. He did a beautiful job packing all those transistors into a tiny space. I love the Tiny Tapeout community. So amazing. One step closer to open source non volatile memory IP. Hooray! ??

???????? ???????????? ?????????????????- ???????? ?????????????? - Today, almost 80 people are spending their Saturday together with DTU Compute | DTU - Technical University of Denmark and the Tiny Tapeout project to get hands-on experience with the process of chip design when creating microchips. Matt Venn, the creator of Tiny Tapeout and an expert in open-source silicon, is leading the four-hour Tiny Tapeout workshop. The participants are a mixed group of students, tech professionels and tech enthusiasts of all experience levels. After the production of the chip, DTU Compute will organise a bring-up party to test the designs. “The Tiny Tapeout project is a game changer in chip design education. Everyone can explore chip design and get their own chip produced by using open-source design tools and for a small amount. In that way, the Tiny Tapeout democratises chip design and production,” says Martin Schoeberl, professor at DTU Compute. This event is sponsored by the new Danish Chips Competence Centre (located at DTU), the Edu4Chip project, Synopsys Inc, and SyoSil. For the past 50 years, DTU has educated most of the engineers working in chip design. At the same time, DTU is the university in Denmark that offers the most courses in digital chip design and chip technology and has the most students in chip-relevant fields. In recent years, DTU Compute has further strengthened its activities in education, specifically in the field of digital chip design. Since 2023, students have been able to choose the new bachelor's programme BSc Computer Engineering, which is primarily academically anchored at DTU Compute but has been developed in close dialogue with DTU Electro. #Edu4Chip – a new joint education for a Master’s in advanced chip design – aims to strengthen Europe's chip design capabilities through harmonised university programmes. Specifically, Edu4Chip provides a cutting-edge Master's degree in advanced chip design in Europe and offers students end-to-end chip design experiences, from conceptualisation to manufacturing and testing. In addition, Edu4Chip offers lifelong learning opportunities for IT professionals. Learn more about it in the chip design theme at DTU Compute's website and visit Edu4Chip on GitHub. Find the links in the comments. #chipdesign #tinytapeout #microchips

What happens when VLSI System Design (VSD) and Semiconductor Fabless Accelerator Lab (SFAL) next-gen technocrats like Dhanvanti Bhavsar and Ankit Mawle take the India Semiconductor Mission to heart? It sparks a vision for India called "#One #Tapeout #Per #Student (OTPs :))" – a dream where every Indian engineering student experiences the journey from #RTL to #silicon - launched by Dr. Satya Gupta from VLSI Society of India (VSI) at VLSI Design Conference 2025 An open-source #RISC-V #Reference #SoC built on an #India-#based #PDK was the missing piece in #Indian #VLSI #education. It was a BIG decision for VSD to open-source its Reference RISC-V SoC design, but we knew it was necessary to bridge this gap. Here's the detailed repo with all scripts https://lnkd.in/gwR2GK7g Thanks to Efabless Corporation fpr caravel, which served as the base design, this vision took shape. It took over 7-8 months, with limited resources, to port the design to #Semiconductor #Laboratory #SCL180nm and complete functional and gate-level simulations—a challenging yet rewarding journey. None of this would have been possible without the relentless support from the ecosystem: 1) Montu Makadia Ji, IRFAN SHAIKH, and Sankalp Singh – for enabling access to Synopsys Inc EDA tools for students across India. 2) #Deep #Sehgal, #Debjyoti #Malik, and Uday Khambete from #Semiconductor #Laboratory (SCL) – for their unwavering support from day one. While this marks an important milestone, the journey is far from over. There’s still DFT, Verification, Physical Design, SoC Implementation, Physical Verification, Tapeout, Tape-in, Packaging, PCB Design, and Testing left to bring this SoC into the hands of every Indian student. If you believe in building #India’s #Semiconductor future and want to contribute - drop a comment. Together, we can turn #One #Tapeout #Per #Student (OTPs) into a reality. Ministry of Electronics and Information Technology India Electronics and Semiconductor Association VLSI Society of India (VSI) Digital India Programme RISC-V International