CHIPS Alliance

What if semiconductor design was as open and collaborative as software development? Open source silicon is reshaping the future of chips, reducing costs, increasing design flexibility, and accelerating innovation. CHIPS Alliance brings together industry leaders, researchers, and engineers to build the future of open source chip design. Moreover, the adoption of open source designs is fostering sustainability, reducing costs, and enhancing flexibility in chip manufacturing. These changes promise to democratize technology, empower smaller nations, and potentially resolve pressing issues like the global chip shortage, paving the way for a more inclusive and innovative future in technology. What is the biggest challenge you see in open source silicon adoption today? #ChipIn Find out more: https://hubs.la/Q03d6VqH0 AMD Antmicro Futurewei Technologies, Inc. Google Intel Corporation Microsoft SiFive VeriSilicon Microelectronics (Shanghai) Co. Ltd. Marvell Technology Meta NVIDIA Microchip Micron Solutions, Inc. #OpenHardware #CHIPDesign #Semiconductors

Our white paper is dropping soon! The future of chip design is open, and our whitepaper will explore how open source innovation is transforming semiconductors. What’s in it? - Open hardware industry trends - Insights on projects like Chisel & ROHD - Governance best practices for open source hardware - Future directions & community impact What you’ll discover: - How open hardware reduces costs & accelerates development - The role of chiplets, FPGA & ASIC tooling, and open-source PDKs in next-gen design - How collaboration & shared R&D are driving industry-wide innovation - The biggest barriers to adoption, and how we’re overcoming them Most importantly, the upcoming White Paper will be versioned, ensuring it evolves with the industry. What would you like to see more of in future revisions? Be sure to follow us on LinkedIn to read it! #ChipIn #ChipsAlliance #OpenHardware

???? Yesterday, at the initiative of minister Beljaarts of Economic Affairs of The Netherlands, 9 European countries have established the #Semicon #Coalition in Brussels. The responsible ministers of #Austria, #Belgium, #Finland, #France, #Germany, #Italy, #Poland, #Spain and #Netherlands have agreed to #strengthen the #European #semiconductor #industry. ??Objectives of the Semicon Coalition are focused on #expanding #production #capacity within the EU and further #strengthening Europe’s current key #leading #positions within the global #semiconductor #value #chain. The initiative is also responding to an ongoing global increase in public investments within this industry. ?? At present, a joint financing of €43?billion is available for the European semiconductor industry through the #EU #Chips #Act. Other large public #multibillion #investments are the CHIPS & Science Act in the US, The Big Fund in China and several substantial initiatives in South Korea, Taiwan and Japan. #Together with the #European #Commission the new #Semicon #Coalition will explore support possibilities within Europe for the long term. Common Statement Kick off Semicon Coalition: https://lnkd.in/eM-ih7Hf #microelectronics #semiconductors #mems #asics #automotive #medical #industrialtech #industrialleadership #industrialinvestment #singlemarket #semiconcoalition Czech National Semiconductor Cluster ALLPROS.eu CHIPS Alliance Chips Joint Undertaking European Semiconductor Industry Association (ESIA)

A new term began on March 1, and we’re delighted to welcome Aaron Cunningham from Google as our newly elected TAC Chair. Aaron is a Technical Program Manager at Google, focused on hardware developer productivity and open source hardware strategy. With over 12 years at Google, he has led initiatives in chip design, maker innovation, and global STEM programs. Shoutout to TAC members Stephano Cetola (Intel Corporation)?Michael Gielda (Antmicro) Robert Chu (Futurewei Technologies, Inc.)?Prabhu Jayanna (AMD), Bryan H. Kelly (Microsoft) Mirjana Videnovic-Misic (Infineon Technologies) who continue to drive open hardware innovation, guide key projects, and strengthen the Chips Alliance community. Join the community slack here: https://lnkd.in/dFVhT85m #ChipIn #ChipsAlliance #opensource #openhardware

What kind of content is most valuable for you? Let us know what you'd like to see from the community this year, or comment below with any other ideas, thanks!

Read about Antmicro's further developments towards #Caliptra 2.0 RoT: support for the #RISCV #VeeR EL2 core with User mode and PMP in the embedded #TockOS: https://lnkd.in/ddTUx7hC AMD Google Microsoft NVIDIA RISC-V International Rob Mains Benjamin S.

Topwrap is an #opensource toolkit for creating top level designs, with reusable user-defined repositories, automatic interconnect generation & an enhanced interface grouping mechanism, helping automate logic design and make informed team decisions. Antmicro RISC-V International https://lnkd.in/dPnFGUqy

Our new #opensource Data Center RDIMM #DDR5 Tester employs an AMD Artix #UltraScale+ #FPGA for better performance and DDR5 rank configuration compatibility, as well as #PCIe, #HDMI & an #I2C / #I3C interface: https://lnkd.in/dT9sQAa6 #Rowhammer Google CHIPS Alliance Rob Mains The Linux Foundation

Find out how we brought #opensource AXI-based #UVM system verification to #Verilator as part of our work on the #Caliptra 2.0 specification. We also included new tests in our CI test suite for checking verification features: https://lnkd.in/dtnXruFg CHIPS Alliance AMD Google Microsoft NVIDIA RISC-V International TRISTAN

The #RISCV community is meeting up in Gothenburg! Join Antmicro for #Caliptra 2.0: how to use #VeeR, #Verilator, #TockOS, #Renode, System Designer, #SystemRDL and an #opensource #I3C core to build your next-gen open source RISC-V based Root of Trust silicon https://lnkd.in/dqDt2qmT RISC-V International CHIPS Alliance AMD Google NVIDIA Microsoft Calista Redmond Lori Servin Rob Mains Bj?rn T?pel