Alan Sguigna uses ChatGPT to analyze Intel Architectural Event Trace (AET) output from our SourcePoint debugger. See the timestamped tracing for MSR reads/writes, SMIs, port ins/outs, divides by zero, and other low-level microarchitectural CPU events as the AAEON Alder Lake target booted from the Secure Kernel to the Windows desktop. ChatGPT provides some amazing insights into system behavior: https://lnkd.in/g7PJybHZ
关于我们
ASSET InterTech is the leading supplier of open tools for embedded instrumentation to engineers doing design validation, test and debug. The ScanWorks platform for embedded instruments provides automation, access and analysis tools in one environment. Users can quickly and easily validate and test semiconductors, circuit boards or entire systems during every phase of a product's lifecycle, including design, manufacturing/repair and field maintenance. The ScanWorks platform for non-intrusive board test and programming technologies, such as boundary-scan test and processor-based functional test and programming, helps engineers improve the quality of their systems by solving limited access problems. ScanWorks Embedded Diagnostics helps designers and field support technicians debug intermittent, irreproducible software and hardware defects in the lab and in the field which are often the source of costly NTFs and customer dissatisfaction. This allows companies to focus on continuous uptime, product differentiation, and high levels of customer service. SourcePoint is a platform of debug and trace tools for C/C++ embedded software and firmware for Intel, AMD and Arm systems. This robust environment features multiple views into code execution so that bugs are found fast and problems resolved quickly.
- 网站
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http://www.asset-intertech.com
ASSET InterTech, Inc.的外部链接
- 所属行业
- 软件开发
- 规模
- 51-200 人
- 总部
- Plano，Texas
- 类型
- 私人持股
- 创立
- 1995
- 领域
- boundary-scan test、processor-controlled test、IBIST、JTAG testing、JTAG、In-System Programming、Embedded Instruments、Embedded Instrumentation、graphical viewer、Embedded Diagnostics、iJTAG、IEEE 1687和software debug and trace
地点
ASSET InterTech, Inc.员工
动态
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A brand new release of SourcePoint, 7.12.68, is now generally available. With 40+ enhancements/fixes, including Arrow Lake and Jasper Lake support, TDX/SEAM debug, SourcePoint + multiple WinDbg instantiations, and many more, it is available to everyone. The Release Notes are in the SourcePoint Academy: https://lnkd.in/gZKJTPG2. Purchase it here: https://lnkd.in/g9UDxYdG
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The recording of our talk at REcon Montreal 2024, JTAG debug of Windows Hyper-V / Secure Kernel with WinDbg and DCI/EXDI, presented together with Ivan Rouzanov, M.S., MBA, GREM, CREA, MCSE, MCTS is now available on YouTube: https://lnkd.in/gcdxUx9F. Turning on subtitles will add clarity due to some recording audio issues.
Recon2024 - Alan Sguigna&Ivan Rouzanov - JTAGDebugOfWindowsHyper VSecureKernelWithWinDbgAndDCIEXDI
https://www.youtube.com/
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Alan Sguigna used the ChatGPT LLM to analyze Intel Processor Trace as Windows transitions from the Secure Kernel to the Normal Kernel during early boot, with very interesting results: https://lnkd.in/gY7TstQa
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John Akin writes about integrating customer IP into an FPGA configuration generated by the ASSET's Embedded Technology Generator (ETG) support application: https://lnkd.in/g9SRPe7R
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Alan Sguigna writes about a microarchitectural difference between Performance cores (P-cores - based on Intel Core architecture) and Efficiency cores (E-cores - based on Intel Atom architecture) in the blog, The Mysterious Behavior of the Intel E-cores: https://lnkd.in/ggf8Xj9k
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Michael R. Johnson posted an excellent webinar recording on how JTAG can span from board-level to system-level, providing high levels of structural test coverage at-scale: https://lnkd.in/gR6K8CTC
When boards are assembled into a system, faults can arise, even with boards that have been individually tested with JTAG. System-Level JTAG, or SJTAG, significantly expands the application potential of JTAG beyond the traditional board-level scope of structural tests. With proper application, JTAG is perfectly suited to detect faults between boards that have been assembled in a system. SJTAG is well-suited for functional tests, device programming, and in-situ diagnostics. Continuing the focus on DFT, I'm re-posting part #3 in the webinar series "Guidelines for System-Level JTAG." I hope this information aids you in achieving greater board and system test coverage! #BOUNDARYSCAN #JTAG #SJTAG #TESTCOVERAGE #DETECTINGFAULTS https://lnkd.in/gp_psxxd
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Calculating the Return on Investment (ROI) for debuggers is difficult. Although your mileage may vary, here's a model for getting approvals from management to upgrade your debugging game: https://lnkd.in/gK8mEyQs
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Inspired by some of the previous articles by Michael R. Johnson, the fifth installment of Unboxing Boundary Scan Test is now online, wherein a Scan Path Verify (SPV) test is created from the beginning on one of ASSET's demonstration boards, the ScanLite 2: https://lnkd.in/gXetcjtd.
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Alan Sguigna's third installment in the blog series, Debugging SMM with JTAG, covers the SMRAM Save State Map, and how it varies with each SMM Entry/Exit: https://lnkd.in/gJSFrpRk
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