Arteris

Introducing FlexGen - Smart NoC IP from Arteris FlexGen, smart network-on-chip IP, revolutionizes complex systems-on-chip designs. It dramatically accelerates chip development while optimizing performance efficiency, addressing the rising demand for faster, more sustainable innovation across applications in AI, automotive, datacenter, consumer electronics, communications and industrial/IoT. Check out the video to learn more ?? #FlexGen #Semiconductor #Innovation #SystemOnChip #NetworkOnChip #Arteris

The growing intricacy of high-end SoC designs is surpassing the human ability to create NoCs without smart assistance. The key drivers for this demand include: ?? Application-specific requirements ?? Cost and performance optimization ?? Miniaturization and integration ?? Data-centric and AI workloads In this article for EDN: Voice of the Engineer, Andy Nightingale, VP of Product Management and Marketing at Arteris, looks into FlexGen, a smart NoC IP alternative for designers. Learn more here ?? https://bit.ly/4ig7Hy5 #FlexGen #Arteris #SystemOnChip #NetworkOnChip #Performance

On April 1-2, Arteris will join the 5th edition of the Automotive Chiplet Forum (ACF) that will take place at Arm in Cambridge, UK. The event will unite leaders from across the automotive and semiconductor industries, with participants from leading OEMs, Tier 1 and Tier 2 suppliers, IDMs, foundries, software companies, and more, to tackle the challenges of automotive chiplets. Laurent Moll, COO at Arteris, will be presenting at the event. His keynote is scheduled for April 1 at 4:30pm. ?? Reach out to us at https://lnkd.in/dJ2TwhWW to book a meeting. #imec #Arteris #SystemOnChip #NetworkOnChip

NEWS ALERT ???: Arteris selected by NEXTCHIP CO.,LTD. to accelerate chip designs for automotive vision technology. Nextchip specializes in developing semiconductor designs for Advanced Driver Assistance Systems (ADAS) and Image Signal Processors (ISP), empowering automotive designers to create high-quality viewing cameras optimized for various lighting conditions, weather scenarios, and adverse conditions. They licensed Arteris' FlexNoC 5 interconnect IP with Functional Safety for their EFREET1 project to bring cutting-edge automotive solutions to market faster and guarantee the low power, high performance, and area efficiency needed. Learn more here ?? https://lnkd.in/dn3hbSe5 #Automotive #ADAS #Arteris #Nextchip #FlexNoC #innovation #semiconductor

In this article for Semiconductor Engineering, Rick Bye, Director of Product Management and Product Marketing at Arteris, talks about the daily struggles IP interconnect engineers face with achieving optimal scalability, performance, and power efficiency. As SoC complexity continues to rise, engineers need solutions that not only optimize performance but also streamline design processes and resource management. FlexGen - smart NoC IP bridges the expertise gap by embedding domain-specific knowledge into automation, enabling design teams to navigate interconnect challenges with greater efficiency. Learn more in the article — ??: https://hubs.ly/Q03c41ML0 #FlexGen #Arteris #SystemOnChip #NetworkOnChip #Automation

The management and integration of numerous IP blocks in modern designs can be complex. In the following article, Mike Gianfagna shares how our latest generation of Magillem Registers helps address the critical challenge of hardware and software integration: https://hubs.ly/Q03bgr3Z0 #MagillemRegisters #semiconductor #innovation #SystemOnChip #NetworkOnChip #Arteris

Chips and systems are becoming more complicated, hence more verification tasks are getting abstracted. So do we need more specialists who are experts in specific tasks, or do we need more generalists who know how to use the tools but don’t necessarily have the depth of understanding? Or do we need some way to balance both? ?? Semiconductor Engineering sat down to discuss that with the panel of experts, including our very own Josh Rensch, Director of Corporate Application Engineering. Read the conversation here: https://lnkd.in/gtKfXCzx #Verification #Arteris #SystemOnChip #NetworkOnChip

Earlier this month Michal Siwinski, CMO at Arteris, spoke at RISC-V International Day Tokyo 2025 Spring. His presentation covered the challenges and solutions of data transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC-V–based SoCs. Watch the full video here to learn more ?? https://hubs.ly/Q03b9n4N0 #Semiconductor #Innovation #SystemOnChip #NetworkOnChip #RISC_V #Arteris

The RISC-V International Instruction Set Architecture (ISA), known for its power, flexibility, low adoption cost and open-source foundation, is experiencing rapid growth across various market segments: automotive, aerospace, defense, networking, telecommunications, datacenters, cloud computing, industrial automation, AI, ML, embedded systems, IoT devices and consumer electronics. In this article, John Min, VP of Customer Success at Arteris, shares how Arteris' NoC soft tiling tech accelerates RISC-V processor cluster design, boosting scalability and reducing errors in complex SoCs: https://hubs.ly/Q03b8GwM0 #Semiconductor #Innovation #SystemOnChip #NetworkOnChip #RISC_V #Arteris

Arteris is joining Synopsys Users Group (SNUG) Silicon Valley 2025. Join Arteris' Guillaume Boillet, Sr. Director of Strategic Marketing, for the poster session or book a meeting with him during the event: https://hubs.ly/Q039bLm60 ?? "Static Verification Methodology for Highly Configurable IP" ?? March 20th, 3:20-4:30pm ?? Santa Clara, USA #SNUG25 #SoC #NoC #Semiconductors #Arteris #AI