Arteris

Introducing FlexGen - Smart NoC IP from Arteris FlexGen, smart network-on-chip IP, revolutionizes complex systems-on-chip designs. It dramatically accelerates chip development while optimizing performance efficiency, addressing the rising demand for faster, more sustainable innovation across applications in AI, automotive, datacenter, consumer electronics, communications and industrial/IoT. Check out the video to learn more ?? #FlexGen #Semiconductor #Innovation #SystemOnChip #NetworkOnChip #Arteris

The management and integration of numerous IP blocks in modern designs can be complex. In the following article, Mike Gianfagna shares how our latest generation of Magillem Registers helps address the critical challenge of hardware and software integration: https://hubs.ly/Q03bgr3Z0 #MagillemRegisters #semiconductor #innovation #SystemOnChip #NetworkOnChip #Arteris

Chips and systems are becoming more complicated, hence more verification tasks are getting abstracted. So do we need more specialists who are experts in specific tasks, or do we need more generalists who know how to use the tools but don’t necessarily have the depth of understanding? Or do we need some way to balance both? ?? Semiconductor Engineering sat down to discuss that with the panel of experts, including our very own Josh Rensch, Director of Corporate Application Engineering. Read the conversation here: https://lnkd.in/gtKfXCzx #Verification #Arteris #SystemOnChip #NetworkOnChip

Earlier this month Michal Siwinski, CMO at Arteris, spoke at RISC-V International Day Tokyo 2025 Spring. His presentation covered the challenges and solutions of data transport architectures for AI and ML in the context of embedded vision architectures and the implementation aspects for NoCs for RISC-V–based SoCs. Watch the full video here to learn more ?? https://hubs.ly/Q03b9n4N0 #Semiconductor #Innovation #SystemOnChip #NetworkOnChip #RISC_V #Arteris

The RISC-V International Instruction Set Architecture (ISA), known for its power, flexibility, low adoption cost and open-source foundation, is experiencing rapid growth across various market segments: automotive, aerospace, defense, networking, telecommunications, datacenters, cloud computing, industrial automation, AI, ML, embedded systems, IoT devices and consumer electronics. In this article, John Min, VP of Customer Success at Arteris, shares how Arteris' NoC soft tiling tech accelerates RISC-V processor cluster design, boosting scalability and reducing errors in complex SoCs: https://hubs.ly/Q03b8GwM0 #Semiconductor #Innovation #SystemOnChip #NetworkOnChip #RISC_V #Arteris

Arteris is joining Synopsys Users Group (SNUG) Silicon Valley 2025. Join Arteris' Guillaume Boillet, Sr. Director of Strategic Marketing, for the poster session or book a meeting with him during the event: https://hubs.ly/Q039bLm60 ?? "Static Verification Methodology for Highly Configurable IP" ?? March 20th, 3:20-4:30pm ?? Santa Clara, USA #SNUG25 #SoC #NoC #Semiconductors #Arteris #AI

Arteris’ FlexGen smart Network-on-Chip (NoC) IP is revolutionizing semiconductor design. As Brian Buntz shares in his recent article FlexGen automates key NoC design phases: ?? Topology generation drops from 20 hours to 4 (a 5x improvement) ?? Initial optimization collapses from 3 hours to 10 minutes (18x faster) ?? Final, physical-aware adjustments plummet from two weeks to just 100 minutes (approximately 20x faster) ?? Beyond just speed, FlexGen reduces wire lengths by up to 30% and latency by 10% Read more here: https://hubs.ly/Q039ddYG0 #FlexGen #Arteris #SystemOnChip #NetworkOnChip #Automation

Arteris’ Magillem Registers technology enables design teams to automate the hardware/software integration process, reducing the development time by 35% while overcoming design complexity challenges and freeing up cycles for new innovations. Successful design teams use Magillem Registers to streamline and optimize workflows with an integrated, single source of truth infrastructure to specify, document, implement, and verify SoC address maps. This approach boosts productivity by promoting efficient IP reuse and ensuring consistency across the relevant design teams. Check out the video to learn more ?? #MagillemRegisters #semiconductor #innovation #SystemOnChip #NetworkOnChip #Arteris

FlexGen dramatically accelerates chip development while optimizing performance efficiency, and addresses the rising demand for faster, more sustainable innovation across a broad set of applications. Neil Tyler at New Electronics shared how FlexGen can reduce manual adjustments by over 90% — enabling optimized NoC topologies in a matter of hours instead of days in his article here: https://hubs.ly/Q037Yb4y0. Learn how FlexGen can transform chip design for complex, next-generation chips by visiting our website: https://hubs.ly/Q037YfZy0 #FlexGen #Arteris #SystemOnChip #NetworkOnChip #Performance

We’re happy to unveil the latest generation of Magillem Registers, the cutting-edge solution designed to revolutionize hardware/software integration for semiconductor design teams ?? This product combines the strengths of Magillem 5 and CSRCompiler into an advanced “single source of truth” for register management. With up to 3x faster performance and 5x scalability, it seamlessly handles designs ranging from IoT devices to the most complex AI-driven multi-die SoCs. "As over 70% of chips face respins, addressing hardware and software integration has become a critical challenge for SoC teams," said K. Charles Janac, President and CEO of Arteris. "Building AI SoCs and FPGAs is expensive and time-consuming, so automation efficiencies are vital to cost control. Our latest release of Magillem Registers ensures that engineering productivity is maximized while project risks are substantially minimized." Learn more about this product here: https://lnkd.in/dDVhkftc #MagillemRegisters #semiconductor #innovation #SystemOnChip #NetworkOnChip #Arteris