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Nanoparticles often undergo thermally driven phase transitions and shape shifting spatial transformation resulting in a thermodynamically stable structures at that temperature. In case of crystalline nanoparticles, these transformations are usually anisotropic, meaning that they are surface dependent. This surface dependency of anisotropic phase transitions is attributed to the work function, surface energy and chemical potential of different crystal facets. When heated, these structures become unstable and begin to transform to an isotropic structure with high thermodynamic stability at a large range of temperature. Investigating these structural phase transitions at atomic scale may provide why some catalysts work terribly at high temperatures and why some catalysts fail to reactivate by thermal treatment. Researchers from Institute for basic science (IBS) have used environmental transmission electron microscopy (ETEM) to observe these structural transformations and geometric shape shifts in gold nanoparticles at atomic scale using phase-contrast microscopy. They studied two types of gold nanoparticles, gold nanorods and triangular gold nanoplates. Above 180°C at 1 mbar O?, surface encapsulating thiol ligands underwent surface desorption exposing the gold surfaces to the oxygen environment. In absence of any surface stabilizing ligands, surfaces atoms started to diffuse around transforming the gold nanoparticles to more thermodynamically stable structures. Nanorods were found to transform to nanoellipsoids whereas nanotriangles were found to transform to nanohexagons through the truncation of their vertices. However, the mechanisms of surface atom diffusion are different in these two cases. In case of nanorods, indiscriminate surface migration of vertex atoms to the sides was found to be driven by the formation of multiple intermediate high-index facets; on the other hand, selective layer-by-layer migration of vertex atoms to the triangular faces was found to have occurred in case of nanotriangles until a hexagonal shape is attained. The thermodynamic driving force here is the minimization of the low-coordinated gold surface atoms that anticipates the final spherical shape of the particles. The triangular geometry of the nanotriangles allowed the {111} surfaces on all faces remain intact during the transition to hexagonal geometry. ETEM experiments were conducted on an aberration-corrected Thermo Fisher Scientific Titan ETEM G2 operated at 300?keV and equipped with a Gatan Inc. UltraScan 1000XP CCD detector. In-situ heating inside the microscope was conducted with a Protochips Fusion in-situ heating TEM holder. Video description is in the comments. Read the interesting findings published in the Journal of Physical Chemistry C. https://lnkd.in/dPHrTx2C #phasetreansitions #surfaceatomdiffusion #phasecontrast #insituTEM #ETEM #Fusion #UltraScan1000XP #electronmicroscopy

OPPSTAR IS BOOSTING PENANG’S IC DESIGN ECOSYSTEM BY ESTABLISHING A POST-SILICON TEST CENTER. Already one of the up and coming IC Design start-ups in Penang, Oppstar Berhad, recognises that there is no IC design if you do not verify that your design actually works. That is called ‘post-silicon testing’ - testing after you get your first silicon back from the fab. Moving up the value chain of semiconductor business means getting into the design space. After all, not many can afford to build, let alone own, a wafer plant to fabricate semicon wafers. Today you can’t get a small one without spending at least US$5 billion. IC design tools - collectively called Electronic Design Automation (EDA) tools - require desk space and an office. And can be set up almost anywhere. Designing a chip is one thing. What do you do when you get your first silicon chips back from the wafer fab?? Test them, of course. Customers of IC design services - and they are almost all MNCs (like Intel Corporation and AMD) - will have their own testing capabilities in-house. These facilities are not cheap, requiring very sophisticated electronics instrumentation and specialised chip-testing equipment. Outside of these multinational companies, currently only research institutes like CEDEC at Universiti Sains Malaysia have such facilities. But they are primarily for post graduate students taking programs there and partners. [see video] That’s where Oppstar comes in, once-again, as a trailblazer. Recognising the semicon boom, they have expanded their IC design capabilities to offer services in? post-silicon testing.? This will be available to customers as an added service and for those who need more capacity when their in-house capabilities are busy. As they expand, this is expected to become a full fledged service open to all, including IC design houses elsewhere, and outside Penang. Malaysia’s semicon & IC design ecosystem takes another step forward. Thank you Soon Lee Yeap, EVP for Silicon Validation, for organising the visit to your new office. Follow ET Tan for more provoking thoughts on tech and humanity, and exciting happenings on semicon. #pearlnessofpenang

Semiconductor Wafer Testing，Probe (CP) We are excited to share a video showcasing Gyro’s AMR robot in action, successfully interfacing with both 300mm wafer FOUP and 200mm Open Cassette to connect with various brands and models of Prober equipment. In this video, our AMR robot is equipped with a 4-slot FOUP and a 4-slot Open Cassette, successfully interfacing with products from the world’s three largest Prober manufacturers—TSK, TEL, and OPUS. What’s even more impressive is that Gyro’s AMR robot can simultaneously handle both FOUP and Open Cassette, connecting to two different Prober systems at the same time. This technological breakthrough highlights Gyro’s powerful capabilities in semiconductor automation, providing our clients with more efficient and flexible solutions. Some of the footage in this video was captured during the installation and debugging process at our client’s site, where our AMRs are actively being integrated into their production lines. This is just a glimpse of Gyro’s collaboration with leading semiconductor companies worldwide over the past few years. From wafers worth tens of thousands of dollars to AI wafers valued at $20 million per FOUP, clients have specifically requested Gyro robots to handle these critical processes. Gyro’s robots are equipped with components sourced from globally recognized suppliers, ensuring high reliability and performance. The trust and satisfaction of our clients are evident, as every customer from our first to the present has returned for additional purchases, demonstrating their confidence in our products. Gyro continues to lead in providing cutting-edge automation solutions for the semiconductor industry, and we remain committed to innovation and excellence in every project.

Breaking Through Silicon Barriers! Here’s a sneak peek at our latest advancement in Through Silicon Via (TSV) technology—precision laser-drilled vias in silicon wafers. These through-holes are the foundation for next-gen 3D integration, enabling faster, smaller, and more efficient semiconductor packaging. At Heisler Semiconductor, we’re pushing the limits of advanced packaging with innovative TSV processing. This is just the beginning—stay tuned as we take these structures from concept to commercialization! What challenges do you see in TSV adoption? Let’s discuss in the comments! #Semiconductors #TSV #AdvancedPackaging #3DIntegration #Innovation #Microelectronics #LaserProcessing #Nanotechnology #Chiplets #ElectronicsManufacturing #WaferProcessing #Tech #Electronics #MEMS #HeterogeneousIntegration #ChipManufacturing

Imitation of the 300mm silicon wafer cleaning process: SC1 Solution Treatment The wafer is treated with an SC1 solution, which is a mixture of ammonium hydroxide (NH?OH), hydrogen peroxide (H?O?), and deionized (DI) water. This step is designed to remove organic contaminants, particles, and some metallic impurities from the wafer surface. The basic environment created by the NH?OH helps dissolve organics, while the oxidizing properties of H?O? aid in breaking down residues. PRX505 Solution Treatment The wafer is then processed with the PRX505 solution, which is a proprietary formulation designed for advanced cleaning or surface modification. This step targets specific contaminants such as residual polymers, more complex organic residues, or metallic ions. Rinsing with Deionized Water After the chemical treatments, the wafer is thoroughly rinsed with deionized (DI) water to remove any remaining chemical residues from the previous steps. This ensures that no harmful substances are left on the wafer surface, which could otherwise affect its performance or contaminate downstream processes. High-Pressure DI Water Jet Cleaning A high-pressure jet of deionized water is used to further clean the wafer surface. This step helps dislodge and remove any stubborn particles or residues that may still be adhering to the wafer. The force of the water stream ensures a more thorough cleaning without damaging the delicate surface of the wafer. Megasonic DI Water Cleaning The wafer undergoes mega-ultrasonic cleaning in deionized water. This process uses high-frequency sound waves to create microscopic bubbles that collapse and release energy, effectively removing even the smallest particles from the wafer surface. Mega-ultrasonic cleaning is particularly useful for achieving high levels of cleanliness and ensuring particle-free surfaces. Drying with High-Purity Nitrogen Gas Finally, the wafer is dried using a directed flow of high-purity nitrogen gas. This step ensures that no water marks or contaminants are left behind after cleaning. The use of high-purity nitrogen prevents oxidation or recontamination of the wafer surface during the drying process, maintaining its pristine condition for further processing or storage. This simulated process ensures a comprehensive cleaning approach, combining chemical treatments, mechanical action, and precise drying techniques to achieve optimal wafer cleanliness.

Die attache with scrubbing: This method of die attach is used for the following purposes: 1?? - to achieve complete wetting of the surfaces of the die and substrate with the interface material (adhesive, solder) 2?? - to reduce void formation in the adhesive joint or solder connection 3?? - to minimize the thickness of the adhesive joint or solder connection As a result, we obtain a reliable connection with a controlled layer thickness of adhesive/solder between the chip and the substrate.

The study explores electrically induced amorphization, a process that has typically relied on pulsed electrical currents in few material systems; however, the researchers discovered a method that allows solid-state amorphization to occur electrically without the need for melting. Researchers demonstrated this unconventional long-range solid-state amorphization in a new ferroic β″-phase of indium selenide nanowires by applying a direct-current bias, highlighting the unique interplay of electric fields, current flow, and piezoelectric stress. The findings reveal complex multimodal coupling mechanisms between ferroic order and external influences, paving the way for the development of new materials and devices tailored for low-power electronic and photonic applications. Read more https://lnkd.in/dwiFq35J More semiconductor news https://abachy.com/news

Researchers have developed a fully integrated photonic processor capable of executing all key computations of deep neural networks using light, paving the way for ultra-fast and energy-efficient AI processing. The optical chip demonstrated the ability to perform machine-learning tasks with over 92 percent accuracy in less than half a nanosecond, making it competitive with traditional electronic computing methods while significantly improving speed and efficiency. The photonic processor uniquely combines linear and nonlinear operations by utilizing nonlinear optical function units (NOFUs), tackling previous challenges in optical systems that required external electronics for nonlinear processing. This innovation holds promise for applications in high-demand fields such as lidar, telecommunications, and scientific research, as the chip can facilitate real-time learning and in situ training while leveraging existing manufacturing processes for scalability. Read more https://lnkd.in/eCUpumd9 More semiconductor news https://abachy.com/news

Intel has announced the resignation of Chief Executive Pat Gelsinger, who stepped down after a board meeting revealed dissatisfaction with the lack of progress on his ambitious turnaround plans. Gelsinger resigned on December 1, less than four years into his tenure, after the board felt that his strategies to restore Intel’s competitive edge in chip manufacturing were not yielding the desired results. The company, once a leading force in Silicon Valley, has significantly fallen behind rivals like Taiwan Semiconductor Manufacturing Co. (TSMC) and Nvidia, the latter of which leads in artificial intelligence chips. https://lnkd.in/eR9w6sEN

The Biden administration has finalized its incentive awards from the Chips Act for Taiwan Semiconductor Manufacturing Co. (TSMC), marking a significant milestone in efforts to revive semiconductor production in the United States. TSMC will receive $6.6 billion in grants, as confirmed by the Department of Commerce. This amount was previously disclosed in a preliminary agreement but is now legally binding, making it the first substantial award under the Chips Act to reach this stage. In addition to the grants, TSMC is set to obtain up to $5 billion in loans, with at least $1 billion of this total expected this year due to the company’s achievement of certain benchmarks. Read more https://lnkd.in/epaGqaaD