What are the most common IC design mistakes and how can you avoid them?

Having separate power and ground layers is important as suggested above. But, creating large "planes" can be detrimental as those would be large radiating surfaces. The highest currents s/b located closest to the power pins. This minimizes the distributed impact. Also, separate paths should be used for signal shielding and contain no supply currents. The long power traces are best constrained to dc currents. Signal regions are more effectively constrained with use of local bypassing/conditioning.

Insufficient ESD protection: Electrostatic discharge (ESD) events can damage ICs. Ensure that your design incorporates proper ESD protection measures, such as ESD diodes and guard rings, to safeguard against ESD events during manufacturing, handling, and operation.

Well, modern power ICs usually have one top level copper layer with 4mOhm/#. All other layers are about 40..100mOhm/# => If you want an effective ground plane for several A you have to use the copper. => since you have only one layer of copper there will never be a plane because you have further traces that carry high current and need the copper as well. In logic it is common to route supplies as a grid in M2 or M3. Does the job - but not good. Bypass caps: available up to 5nF, max 5V. That's all. Ferrite beads: not available on chip. On chip inductors: 1nH already is a lot. Q about 5. Typical solutions done on chip: star point routing. But this is all hand crafted. Section needs rework.

Two problems in RF frequency boards. Any frequency current wants to find its path with the least impedence. The ground plane and negative return path are best designed with return path following the exact route of the positive signal wire. extra ground plane beyond that of the return signal path isn't necessarily required. 2. EMF is next consideration. If you create an antenna based on frequency and electrical length based on capacitance/inductance then every other wire of the right electrical length acts as a receiver. Then you have induced noise all over the place.

Ho hummm….a ground plane for high precision analog is a disaster. There is simply no way to control the drops with a ground plane. There needs to be star points. Typically one might have a star fanning out to 10 to 20 individual routes for voltage references, same for a vmid power supply and same for the analog grounds. It’s the only way to get 10uv dc precision

Having the right simulation tools and being able to correctly interpret the results is very important. Also, it is important to know which technique is more adequate for every problem. If it is a simple planar structure, looking at S-parameters might be enough. If dealing with complex structures, consisting of multiple vias interconnection for example, postprocessing S-parameters to be visualised in the time domain (Time Domain Reflectometer - TDR) is of great help and one can identify exactly where improvement is required. For some applications (mostly digital data links), looking at an Eye Diagram will be the preferred method.

Please share your insights into "proper termination techniques" applied to, say, LPDDR routing. Also, it would be great to learn about avoiding "parasitic" inductance (~1nH/mm), capacitance (~10fF/mm) and resistance (=L/C/Q). Much appreciated !

Matched termination on chip makes sense for 10GHz or more. For lower frequencies I guess nobody will accept the dissipation. Shielding: You can build coax like structures. But the space needed for wires explodes (typ. factor 9. Three times the width and you block 3 layers in stead of one) and the charging losses of fast clocked traces go up (about factor 9) dramatically. Tools: You don't have the disk space to do a full chip RC(L) back annotation. Back annotation is nice - for may be 100 componets (some TB of data, some days CPU time for one simulation run for a simple clocked comparator , 10000 clock cycles is a rough guess.)

There are some who still must have a central bias generator, however these are crosstalk minefields. With the demand for lower bias currents and lower standby currents these individual currents have been reduced dramatically further increasing the risk of crosstalk. From a design integrity standpoint I would eliminate the central bias generator. I have used local bias generator, distributing a bias voltage, since even for a local generator crosstalk to bias current lines is super-sensitive as well as to any other moving signal.

The absolute worst crosstalk issue is central biasing, it is a nightmare for layout to prevent crosstalk, and an even harder thing to simulate on large PMIC’s. Always run extracted simulations, because you never know what is going to hit you. Avoid using 5v logic as the weak drive has the greatest logic sensitivity. Mixing voltage domains in the same bus is also a recipe for crosstalk.

All would agree that synchronization between domain is critical, but people often overlook it as it is difficult to catch in simulation. There are some tools that help, but it can be improved quite a bit with some discipline. Simply adding the clock domain name to signals, and then adding some unique key to any block that can cross domains, i.e. all synchronizers begin with "i_sync_*", all 2-way handshakes must go through a block called "i_hand_*" and so on. This alone makes a simple visual key to help designers. It also makes it easy for a STA tool to report any paths between domains that are not properly handled.

One of the big forgotten are usually the reset signals when referring to timing. Keeping them clean of timing issues is of vital importance too -All async resets must have proper reset synchronization for each clock domain -Take care for glitches (do not use combo logic from related signals). - Differentiate async resets vs synch clear conditions (it is key to keep async reset networks as clean and small as possible). - You may need specific reset deassertion sequencing for complex systems - Combo loops through async resets are not easy to catch. Ensure you provide a min assertion time for generated resets. Adhere always to good design practices, use proper signal naming and ensure you have clean lint/CDC checks

Simply adding a synchronizer does not guarantee the elimination of metastability. We must also consider the probability of metastability and its impact on the system. Proper analysis includes considering the MTBF (Mean Time Between Failures) related to synchronizers.

Now there arises an impression within me that this text is AI generated... Or is it because LinkedIn offered me a German translation to read

One point to keep in mind in that package parasitic elements are one to two orders of magnitude larger than chip level parasitic elements and that PCB parasitic elements are again one to two orders of magnitude larger than package level parasitic elements. And none of these are considered during chip design.

During schematic design, it is crucial that the designer knows how sensitive performance is with respect to parasitics in certain nodes of the design. Doing a sensitivity study before layouting is important to avoid too many iterations in the future. EDA tools allow designers nowadays to annotate constraints about parasitic resistance and capacitance in nodes of their choice.

Mismatch or inconsistency between your layout and fabrication process can cause physical defects, performance degradation, or yield loss. To prevent these errors, you should use design rules and constraints that are compatible with your fabrication technology and specifications. Additionally, LVS and DRC tools can verify and correct any errors or violations in your layout. Parasitic extraction and simulation tools should be used to account for the parasitic effects of your layout and fabrication process on your circuit behavior and performance. Finally, DFM and DFT techniques can be used to enhance the robustness and reliability of your IC design and fabrication process

After many years of design I have come to the conclusion that electrons are not fussy and neatness is not that critical. However using the correct structures such as common centroids goes a long way to improving offset. Short resistors are another all to common mistake degrading performance and potentially exceeding lifetime drift targets. The optimum length is inversely proportional to the resistivity of the poly used. Reducing node size unfortunately does not change this. It is all about end resistance, and its variation. Poly has never had a particularly low contact resistance, and it tends to change over lifetime. A good rule of thumb is 0.1% contact resistance to resistor for precision resistors.

My gotcha was in one of my early PMIC’s I ground only by the guidelines. This was a mistake as I ended up with insufficient grounding and failed latch-up testing. Since substrate contact is an early part of the process, I ended scrapping the lot of wafers and fixing the substrate contacts. More modern PDK’s guide you to add way more substrate contacts, and rightly so.

Although Analog DfT is not as known and researched as its digital counterpart, there are some good practices that can be followed by designers to increase the design's reliability. For example, in analog test busses, use a T-switch configuration instead of a single transmission gate. A T-switch consists of three switches; two in series and one providing a ground to the midpoint of the series connected switches. The grounding switch is closed any time the series switches are opened, thereby shunting any potential crosstalk signals to ground. The only problem is that the resulting switch always presents a small capacitive load to ground on the node to be sensed. Fortunately, in many cases the extra load capacitance is entirely acceptable.

Having the correct test equipment is critical to perform functional design analysis and trouble shooting. Sometimes specialized equipment is required, e.g., radiated emi or high energy transient suppression. In addition to the equipment, items to control environment and/or eliminate random, external interference, such as temperature chambers, Faraday cages is often necessary. The goal of all testing is to spot/identify design weaknesses, verify performance requirements, and identify operational margins.

Besides having proper equipment for testing the prototype/product, it is also important to consider designing built-in self-test (BIST) circuitry around the system. Also, analog and DC test buses in important bias nodes (or replicas of these to not disturb them) might give important information in case the circuit shows unexpected performance in noise, distortion, gain, etc.

With small geometry processes there is very little probing that can be done. A good analog mux is essential for both debug and chip verification. Analyze the design to ensure there is enough test points on the mux. It is important to limit the local mux to no more than 1 of 8. So a mux tree is a must.

May be not what else, but what's first... Everything has to refer to a design specification. The first and the most important step in IC design is defining the goal with an extensive specification. And then, the second most important thing is a strong top-down design methodology. All the various techniques and trick have to fit in a methodology framework.

I’ve witnessed the consequences of overlooking specifications, truly catastrophic. Too often, there’s a blame game; Physical Design blaming IP developers for incorrect constraints, while IP Designers blame implementation team for not understanding the specifications in the first place. Different interpretation of the specifications, leading to a misalignment with the actual project requirements. Implementation team doesn’t delve deep into the specifications, they might miss crucial details, resulting in a flawed design. A solid understanding of specifications is the cornerstone for a successful project outcomes. Let’s break the cycle of finger-pointing by fostering clear communication and ensuring everyone is on the same page.

I agree strongly with Jean-Francis. Understanding and interpreting the spec is critical. Where we go from there is also really important. the goal of any IC design is to meet the required spec in the smallest area possible. The general rule almost always applies, Price Wins, and the smallest die allows the cheapest selling price. As a designer it is discouraging to have your work discarded because the chip was too expensive for the market. for a PMIC or any system type chip, it is no good for one cell to be small if the rest do not follow, this must be an across the board mentality.

I've found that there is too little design effort put into the "simple" interfaces. Memory, SerDes get lots of attention. Low speed interfaces get treated as simple and the time needed to verify gets short cut. Thus the lower speed interfaces in many cases can be the can be the cause of design iterations

Believing that what you see in documents, simulations are the reality of device operation. Especially when the device is outside its application-normal ranges, or when trying to do low power analog design on a "digital" technology's kit. There are still compact models which fail entirely to emulate normal junction breakdowns. Or throw flags as a substitute for realism. Published schematics often lie by omission or intent. "I find your lack of faith disturbing" - Darth Vader, and corporate CAD directors