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How do you perform STA for low-power and high-performance designs?

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Static timing analysis (STA) is a crucial skill for designing reliable and efficient digital circuits. It helps you verify that your design meets the timing constraints and avoids errors like glitches, hold violations, or setup violations. But how do you perform STA for low-power and high-performance designs? In this article, we will cover some key aspects and techniques of STA for these challenging scenarios.

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1 Power-aware STA

Low-power designs often use techniques like clock gating, power gating, voltage scaling, or multi-threshold CMOS to reduce the power consumption of the circuit. However, these techniques also introduce new sources of timing variation and complexity that need to be accounted for in STA. Power-aware STA is a methodology that considers the effects of power modes, power domains, level shifters, isolation cells, retention cells, and other low-power elements on the timing behavior of the circuit. It requires accurate power models, power-aware libraries, and power-aware constraints to perform accurate analysis and optimization.

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2 Timing corners

High-performance designs often operate at high frequencies and need to meet tight timing margins. However, the timing behavior of the circuit can vary significantly depending on the process, voltage, and temperature (PVT) conditions. To account for these variations, STA uses timing corners, which are combinations of PVT values that represent the worst-case and best-case scenarios for timing analysis. Typically, STA performs analysis for multiple timing corners to ensure that the design meets the timing requirements across all possible operating conditions.

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3 Timing margin

Timing margin is the amount of time by which a signal arrives earlier or later than the required time at a given point in the circuit. It is a measure of how robust the design is against timing variations and errors. A positive timing margin means that the signal arrives early enough to avoid setup violations, while a negative timing margin means that the signal arrives too late and causes setup violations. A zero timing margin means that the signal arrives exactly at the required time. Ideally, you want to have a positive timing margin for all signals in your design, but not too large to waste power or area.

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4 Timing optimization

Timing optimization is the process of improving the timing performance of a circuit by adjusting parameters or structure. It can be done at various levels of abstraction, such as logic synthesis, placement, routing, or post-layout. Common techniques for timing optimization include sizing, buffering, cloning, and retiming. For instance, changing the width or length of transistors or gates to increase or decrease their drive strength and speed; inserting buffers or inverters along a signal path to reduce the capacitive load and improve the signal integrity; duplicating a logic cell or a subcircuit to reduce fanout and delay of a critical path; and moving registers or flip-flops across logic gates to balance delay between clock-to-Q and combinational logic.

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5 Timing closure

Achieving timing closure is the ultimate goal of STA and optimization. It means that the design meets all the timing constraints and has no timing violations for all the timing corners. This can be difficult for low-power and high-performance designs, as they often have complex timing constraints, multiple power domains, and large variations. To reach timing closure, you should use effective tools, methods, and strategies such as incremental STA, hierarchical STA, and timing signoff. Incremental STA only analyzes parts of the design that have changed since the last analysis to save time and resources. Hierarchical STA works on different levels of hierarchy from blocks to subsystems to top-level to reduce complexity and improve accuracy. Timing signoff uses the most accurate models, libraries, and constraints to verify that the design meets specifications and is ready for fabrication.

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Jamie Chen

Sr Principal Application Engineer at Cadence
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In today's low power designs, the voltage of the power supply has been pushed to very low, quite often below 1.0V. Timing is NOT closed if the power supply voltage IR Drop is not considered for these low power, low supply voltage designs. The advanced chip designer needs to derate the voltage drop for each instance before running STA for timing closure.

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6 Here’s what else to consider

This is a space to share examples, stories, or insights that don’t fit into any of the previous sections. What else would you like to add?

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Mikael Arnfelt
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Don't forget about system level power integrity aspects. In today's low voltage and extreme high logic density designs it is not possible to only consider on-die the static and dynamic voltage drop. You should also consider the PDN (Power Delivery System) of your complete system including package, board and PMIC effects. Rapid changes between low and high activity on the die may lead to supply rail noise that in worst case breaks your whole voltage margin and thereby timing budget. Careful power profiling of your design along with system level optimization of die, package and board may be required to claim timing closure.

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How do you perform STA for low-power and high-performance designs?

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1 Power-aware STA

2 Timing corners

3 Timing margin

4 Timing optimization

5 Timing closure

6 Here’s what else to consider

Static Timing Analysis

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